The Experts below are selected from a list of 4389 Experts worldwide ranked by ideXlab platform

N R Shanbhag - One of the best experts on this subject based on the ideXlab platform.

  • a 19 4 nj decision 364 k decisions s in memory random forest multi class inference accelerator
    IEEE Journal of Solid-state Circuits, 2018
    Co-Authors: Mingu Kang, Sujan K Gonugondla, Sungmin Lim, N R Shanbhag
    Abstract:

    This paper presents an integrated circuit (IC) realization of a random forest (RF) machine learning classifier in a 65-nm CMOS. Algorithm, architecture, and circuits are co-optimized to achieve aggressive energy and delay benefits by taking advantage of the inherent error resiliency derived from the ensemble nature of an RF classifier. Deterministic sub-sampling (DSS) and regularized decision trees reduce interconnect complexity, and avoid irregular memory access patterns and computations, thereby reducing the energy-delay product (EDP). The prototype IC also employs low-swing analog in-memory computations embedded in a standard 6T SRAM to enable massively parallel tree node comparisons, thereby minimizing the memory fetches and reducing the EDP further. The 65-nm CMOS prototype IC achieves a $3.1{\times }$ and $2.2{\times }$ improved energy efficiency and throughput leading to $6.8{\times }$ lower EDP compared to a conventional digital system at the same accuracies of 94% and 97.5% for two tasks: 1) eight-class traffic sign recognition and 2) face detection, respectively.

  • an in memory vlsi architecture for convolutional neural networks
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2018
    Co-Authors: Mingu Kang, Sujan K Gonugondla, Sungmin Lim, N R Shanbhag
    Abstract:

    This paper presents an energy-efficient and high throughput architecture for convolutional neural networks (CNN). Architectural and circuit techniques are proposed to address the dominant energy and delay costs associated with data movement in CNNs. The proposed architecture employs a deep in-memory architecture, to embed energy-efficient low swing mixed-signal computations in the periphery of the SRAM bitcell array. An efficient data access pattern and a mixed-signal multiplier are proposed to exploit data reuse opportunities in convolution. Silicon-validated energy, delay, and behavioral models of the proposed architecture are developed and employed to perform large-scale system simulations. System-level simulations using these models show >97% detection accuracy on the MNIST data set, along with $4.9\times $ and $2.4\times $ improvements in energy efficiency and throughput, respectively, leading to $11.9\times $ reduction in energy-delay product as compared with a conventional (SRAM + digital processor) architecture.

  • a 19 4 nj decision 364k decisions s in memory random forest classifier in 6t sram array
    European Solid-State Circuits Conference, 2017
    Co-Authors: Mingu Kang, Sujan K Gonugondla, N R Shanbhag
    Abstract:

    This paper presents IC realization of a random forest (RF) machine learning classifier. Algorithm-architecture-circuit is co-optimized to minimize the energy-delay product (EDP). Deterministic subsampling (DSS) and balanced decision trees result in reduced interconnect complexity and avoid irregular memory accesses. Low-swing analog in-memory computations embedded in a standard 6T SRAM enable massively parallel processing thereby minimizing the memory fetches and reducing the EDP further. The 65nm CMOS prototype achieves a 6.8× lower EDP compared to a conventional design at the same accuracy (94%) for an 8-class traffic sign recognition problem.

  • an energy efficient memory based high throughput vlsi architecture for convolutional networks
    International Conference on Acoustics Speech and Signal Processing, 2015
    Co-Authors: Mingu Kang, Sujan K Gonugondla, Minsun Keel, N R Shanbhag
    Abstract:

    In this paper, an energy efficient, memory-intensive, and high throughput VLSI architecture is proposed for convolutional networks (C-Net) by employing compute memory (CM) [1], where computation is deeply embedded into the memory (SRAM). Behavioral models incorporating CM's circuit non-idealities and energy models in 45nm SOI CMOS are presented. System-level simulations using these models demonstrate that the probability of handwritten digit recognition P r > 0.99 can be achieved using the MNIST database [2], along with a 24.5× reduced energy delay product, a 5.0× reduced energy, and a 4.9× higher throughput as compared to the conventional system.

  • coding for system on chip networks a unified framework
    Design Automation Conference, 2004
    Co-Authors: S R Sridhara, N R Shanbhag
    Abstract:

    In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of trade-offs between bus delay, codec latency, power, area, and reliability. Simulation results, for a 1-cm 32-bit bus in a 0.18-$mu$m CMOS technology, show that 31 reduction in energy and 62 reduction in energy-delay product are achievable.

Alexander V Veidenbaum - One of the best experts on this subject based on the ideXlab platform.

  • dynamic register file resizing and frequency scaling to improve embedded processor performance and energy delay efficiency
    Design Automation Conference, 2008
    Co-Authors: Houman Homayoun, Sudeep Pasricha, Mohammad Makhzan, Alexander V Veidenbaum
    Abstract:

    With CMOS scaling leading to ever increasing levels of transistor integration on a chip, designers of high-performance embedded processors have ample area available to increase processor resources in order to improve performance. However, increasing resource sizes can increase power dissipation and also reduce access time, which can limit maximum achievable operating frequency. In this paper, we explore optimizations for the processor register file (RF), to improve performance and reduce the energy-delay product. We show that while increasing the size of the RF can potentially increase the IPC, overall it results in an increase in program execution time. In response we propose L2MRFS -- a dynamic register file resizing scheme in tandem with frequency scaling, which exploits L2 cache misses to noticeably improve processor performance (11% on average) and also significantly reduce the energy-delay product (7%).

  • fast speculative address generation and way caching for reducing l1 data cache energy
    International Conference on Computer Design, 2006
    Co-Authors: Dan Nicolaescu, Alexander V Veidenbaum, Babak Salamat, Mateo Valero
    Abstract:

    L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access latency can be affected as well, leading to an increase in overall energy consumption due to increased execution time. At the same time, the static energy consumption of the cache increases significantly with each new process generation. This paper proposes a new approach to reduce the overall L1 cache energy consumption using a combination of way caching and fast, speculative address generation. A 16-entry way cache storing a 3-bit way number for recently accessed L1 data cache lines is shown sufficient to significantly reduce both static and dynamic energy consumption of the L1 cache. Fast speculative address generation helps to hide the way cache access latency and is highly accurate. The L1 cache energy-delay product is reduced by 10% compared to using the way cache alone and by 37% compared to the use of multiple MRU technique.

  • energy effective instruction fetch unit for wide issue processors
    Lecture Notes in Computer Science, 2005
    Co-Authors: Juan L Aragon, Alexander V Veidenbaum
    Abstract:

    Continuing advances in semiconductor technology and demand for higher performance will lead to more powerful, superpipelined and wider issue processors. Instruction caches in such processors will consume a significant fraction of the on-chip energy due to very wide fetch on each cycle. This paper proposes a new energy-effective design of the fetch unit that exploits the fact that not all instructions in a given I-cache fetch line are used due to taken branches. A Fetch Mask Determination unit is proposed to detect which instructions in an I-cache access will actually be used to avoid fetching any of the other instructions. The solution is evaluated for a 4-, 8- and 16-wide issue processor in 100nm technology. Results show an average improvement in the I-cache energy-delay product of 20% for the 8-wide issue processor and 33% for the 16-wide issue processor for the SPEC2000, with no negative impact on performance.

  • Reducing Data Cache energy Consumption via Cached Load/Store Queue
    2003
    Co-Authors: Dan Nicolaescu, Alexander V Veidenbaum, Alex Nicolau
    Abstract:

    High-performance processors use a large set--associative L1 data cache with multiple ports. As clock speeds and size increase such a cache consumes a significant percentage of the total processor energy. This paper proposes a method of saving energy by reducing the number of data cache accesses. It does so by modifying the Load/Store Queue design to allow "caching" of previously accessed data values on both loads and stores after the corresponding memory access instruction has been committed. It is shown that a 32-entry modified LSQ design allows an average of 38.5% of the loads in the SpecINT95 benchmarks and 18.9% in the SpecFP95 benchmarks to get their data from the LSQ. The reduction in the number of L1 cache accesses results in up to a 40% reduction in the L1 data cache energy consumption and in an up to a 16% improvement in the energy--delay product while requiring almost no additional hardware or complex control logic

Mingu Kang - One of the best experts on this subject based on the ideXlab platform.

  • a 19 4 nj decision 364 k decisions s in memory random forest multi class inference accelerator
    IEEE Journal of Solid-state Circuits, 2018
    Co-Authors: Mingu Kang, Sujan K Gonugondla, Sungmin Lim, N R Shanbhag
    Abstract:

    This paper presents an integrated circuit (IC) realization of a random forest (RF) machine learning classifier in a 65-nm CMOS. Algorithm, architecture, and circuits are co-optimized to achieve aggressive energy and delay benefits by taking advantage of the inherent error resiliency derived from the ensemble nature of an RF classifier. Deterministic sub-sampling (DSS) and regularized decision trees reduce interconnect complexity, and avoid irregular memory access patterns and computations, thereby reducing the energy-delay product (EDP). The prototype IC also employs low-swing analog in-memory computations embedded in a standard 6T SRAM to enable massively parallel tree node comparisons, thereby minimizing the memory fetches and reducing the EDP further. The 65-nm CMOS prototype IC achieves a $3.1{\times }$ and $2.2{\times }$ improved energy efficiency and throughput leading to $6.8{\times }$ lower EDP compared to a conventional digital system at the same accuracies of 94% and 97.5% for two tasks: 1) eight-class traffic sign recognition and 2) face detection, respectively.

  • an in memory vlsi architecture for convolutional neural networks
    IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2018
    Co-Authors: Mingu Kang, Sujan K Gonugondla, Sungmin Lim, N R Shanbhag
    Abstract:

    This paper presents an energy-efficient and high throughput architecture for convolutional neural networks (CNN). Architectural and circuit techniques are proposed to address the dominant energy and delay costs associated with data movement in CNNs. The proposed architecture employs a deep in-memory architecture, to embed energy-efficient low swing mixed-signal computations in the periphery of the SRAM bitcell array. An efficient data access pattern and a mixed-signal multiplier are proposed to exploit data reuse opportunities in convolution. Silicon-validated energy, delay, and behavioral models of the proposed architecture are developed and employed to perform large-scale system simulations. System-level simulations using these models show >97% detection accuracy on the MNIST data set, along with $4.9\times $ and $2.4\times $ improvements in energy efficiency and throughput, respectively, leading to $11.9\times $ reduction in energy-delay product as compared with a conventional (SRAM + digital processor) architecture.

  • a 19 4 nj decision 364k decisions s in memory random forest classifier in 6t sram array
    European Solid-State Circuits Conference, 2017
    Co-Authors: Mingu Kang, Sujan K Gonugondla, N R Shanbhag
    Abstract:

    This paper presents IC realization of a random forest (RF) machine learning classifier. Algorithm-architecture-circuit is co-optimized to minimize the energy-delay product (EDP). Deterministic subsampling (DSS) and balanced decision trees result in reduced interconnect complexity and avoid irregular memory accesses. Low-swing analog in-memory computations embedded in a standard 6T SRAM enable massively parallel processing thereby minimizing the memory fetches and reducing the EDP further. The 65nm CMOS prototype achieves a 6.8× lower EDP compared to a conventional design at the same accuracy (94%) for an 8-class traffic sign recognition problem.

  • an energy efficient memory based high throughput vlsi architecture for convolutional networks
    International Conference on Acoustics Speech and Signal Processing, 2015
    Co-Authors: Mingu Kang, Sujan K Gonugondla, Minsun Keel, N R Shanbhag
    Abstract:

    In this paper, an energy efficient, memory-intensive, and high throughput VLSI architecture is proposed for convolutional networks (C-Net) by employing compute memory (CM) [1], where computation is deeply embedded into the memory (SRAM). Behavioral models incorporating CM's circuit non-idealities and energy models in 45nm SOI CMOS are presented. System-level simulations using these models demonstrate that the probability of handwritten digit recognition P r > 0.99 can be achieved using the MNIST database [2], along with a 24.5× reduced energy delay product, a 5.0× reduced energy, and a 4.9× higher throughput as compared to the conventional system.

Ian A Young - One of the best experts on this subject based on the ideXlab platform.

  • energy delay performance of giant spin hall effect switching for dense magnetic memory
    Applied Physics Express, 2014
    Co-Authors: Sasikanth Manipatruni, Dmitri E Nikonov, Ian A Young
    Abstract:

    We show that the giant spin Hall effect (GSHE) magnetoresistive random access memory (MRAM) can enable better energy delay and voltage performance than MTJ spin torque devices at 10?30 nm scaled nanomagnet dimensions. We propose a dense bit cell composed of a folded electrode to enable scaling to sub-10 nm CMOS. We derive the energy-delay trajectory and energy-delay product of GSHE and MTJ devices with an energy minimum at the magnetic characteristic time. Optimized GSHE devices with PMA can enable low voltage (<0.1 V), scaled dimensions, and fast switching time (100 ps) at an average switching energy approaching 100 aJ/bit.

  • charge resistance approach to benchmarking performance of beyond cmos information processing devices
    IEEE Transactions on Nanotechnology, 2014
    Co-Authors: Angik Sarkar, Dmitri E Nikonov, Ian A Young, Behtash Behinaein, Supriyo Datta
    Abstract:

    Multiple beyond-CMOS information processing devices are presently under active research and require methods of benchmarking them. A new approach for calculating the performance metric, energy-delay product, of such devices is proposed. The approach involves estimating the device properties of resistance and switching charge, rather than dynamic evolution characteristics, such as switching energy and time. The application of this approach to a wide class of charge-based and noncharge-based devices is discussed. The approach suggests pathways for improving the performance of `beyond-CMOS' devices and a new realistic limit for energy-delay product in terms of the Planck's constant.

  • voltage and energy delay performance of giant spin hall effect switching for magnetic memory and logic
    arXiv: Mesoscale and Nanoscale Physics, 2013
    Co-Authors: Sasikanth Manipatruni, Dmitri E Nikonov, Ian A Young
    Abstract:

    In this letter, we show that Giant Spin Hall Effect (GSHE) MRAM can enable better energy- delay and voltage performance than traditional MTJ based spin torque devices at scaled nanomagnet dimensions (10-30 nm). Firstly, we derive the effect of dimensional scaling on spin injection efficiency, voltage-delay and energy-delay of spin torque switching using MTJs and GSHE and identify the optimum electrode geometry for low operating voltage ( 10 GHz) operation. We show that effective spin injection efficiency >100 % can be obtained using optimum spin hall electrode thickness for 30 nm nanomagnet widths. Finally, we derive the energy-delay trajectory of GSHE and MTJ devices to calculate the energy-delay product of GSHE and MTJ devices with an energy minimum at the characteristic time of the magnets. Optimized GSHE devices when combined with PMA can enable MRAM with scaled nanomagnets (30 nm X 60 nm), ultra-low voltage operation (< 0.1 V), fast switching times (10 ps) and switching energy as low as 100 aJ/bit.

Alok Choudhary - One of the best experts on this subject based on the ideXlab platform.

  • compiler directed scratch pad memory optimization for embedded multiprocessors
    International Symposium on Low Power Electronics and Design, 2004
    Co-Authors: Mahmut Kandemir, Jothi Ramanujam, Alok Choudhary, I Kadayif, I Kolcu
    Abstract:

    This paper presents a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets at reducing extra off-chip memory accesses caused by interprocessor communication. This is achieved by increasing the application-wide reuse of data that resides in scratch-pad memories of processors. Our results obtained using four array-intensive image processing applications indicate that exploiting interprocessor data sharing can reduce energy-delay product significantly on a four-processor embedded system.

  • exploiting shared scratch pad memory space in embedded multiprocessor systems
    Design Automation Conference, 2002
    Co-Authors: Mahmut Kandemir, Jothi Ramanujam, Alok Choudhary
    Abstract:

    In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets the reduction of extra off-chip memory accesses caused by inter-processor communication. This is achieved by increasing the application-wide reuse of data that resides in the scratch-pad memories of processors. Our experimental results obtained on four array-intensive image processing applications indicate that exploiting inter-processor data sharing can reduce the energy-delay product by as much as 33.8% (and 24.3% on average) on a four-processor embedded system. The results also show that the proposed strategy is robust in the sense that it gives consistently good results over a wide range of several architectural parameters.