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Junyan Ren - One of the best experts on this subject based on the ideXlab platform.
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a 800 ms s 12 bit ringamp based sar assisted pipeline adc with gain Error Cancellation
International Symposium on Circuits and Systems, 2018Co-Authors: Yongzhen Chen, Yuefeng Cao, Junyan RenAbstract:A SAR assisted pipeline ADC with an inter-stage ring amplifier is an energy efficient structure. The ring amplifier is an alternative to an OTA for its low power consumption and large output swing. To improve the accuracy of the common-mode feedback circuit and speed up the settling of the ring amplifier, an improved bias-enhanced ring amplifier is proposed. Additionally, to alleviate the loss of the ring amplifier's DC gain in the nanoscale CMOS process and to migrate the dynamic offset caused by the non-ideal switches, a gain Error Cancellation method is introduced by adding a feedforward amplification path. Designed in a 1 V 28 nm CMOS process, two cascaded pipeline stages and two time-interleaved SAR sub-ADCs make up the ADC. In the post layout simulation that includes transient noise and other non-ideal factors, this 12-bit ADC achieves 60.9dB SNDR and 72dB SFDR at a Nyquist input and sampled at 800 MS/s without analog Cancellation, consuming 16.02mW. With gain Error Cancellation, SFDR is improved by more than 3dB.
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ISCAS - A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018Co-Authors: Yongzhen Chen, Yuefeng Cao, Junyan RenAbstract:A SAR assisted pipeline ADC with an inter-stage ring amplifier is an energy efficient structure. The ring amplifier is an alternative to an OTA for its low power consumption and large output swing. To improve the accuracy of the common-mode feedback circuit and speed up the settling of the ring amplifier, an improved bias-enhanced ring amplifier is proposed. Additionally, to alleviate the loss of the ring amplifier's DC gain in the nanoscale CMOS process and to migrate the dynamic offset caused by the non-ideal switches, a gain Error Cancellation method is introduced by adding a feedforward amplification path. Designed in a 1 V 28 nm CMOS process, two cascaded pipeline stages and two time-interleaved SAR sub-ADCs make up the ADC. In the post layout simulation that includes transient noise and other non-ideal factors, this 12-bit ADC achieves 60.9dB SNDR and 72dB SFDR at a Nyquist input and sampled at 800 MS/s without analog Cancellation, consuming 16.02mW. With gain Error Cancellation, SFDR is improved by more than 3dB.
N R Shanbhag - One of the best experts on this subject based on the ideXlab platform.
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perfect Error compensation via algorithmic Error Cancellation
International Conference on Acoustics Speech and Signal Processing, 2016Co-Authors: Sujan K Gonugondla, Byonghyo Shim, N R ShanbhagAbstract:This paper presents a novel statistical Error compensation (SEC) technique — algorithmic Error Cancellation (AEC)-for designing robust and energy-efficient signal processing and machine learning kernels on scaled process technologies. AEC exhibits a perfect Error compensation (PEC) property, i.e., it is able to achieve a post-compensation Error rate equal to zero. AEC generates a maximum likelihood (ML) estimate of the hardware Error and employs it for Error Cancellation. AEC is applied to a voltage overscaled 45-tap, 45nm CMOS finite impulse response (FIR) filter employed in a EEG seizure detection system. AEC is shown to perfectly compensate for Errors in the main FIR block and its reduced precision replica when they make Errors at a rate of up to 73% and 98%, respectively. The AEC-based FIR is compared with an uncompensated architecture, and a fast architecture. AEC's Error compensation capability enables it to achieve a 31.5% (at same supply voltage) and 19.7% (at same energy) speed-up over the uncompensated architecture, and a 8. 9% speed-up over a fast architecture at the same energy consumption. At fd, k = 452.3 MHz, AEC results in a 27.7% and 12.4% energy savings over the uncompensated and fast architectures, respectively.
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ICASSP - Perfect Error compensation via algorithmic Error Cancellation
2016 IEEE International Conference on Acoustics Speech and Signal Processing (ICASSP), 2016Co-Authors: Sujan K Gonugondla, Byonghyo Shim, N R ShanbhagAbstract:This paper presents a novel statistical Error compensation (SEC) technique — algorithmic Error Cancellation (AEC)-for designing robust and energy-efficient signal processing and machine learning kernels on scaled process technologies. AEC exhibits a perfect Error compensation (PEC) property, i.e., it is able to achieve a post-compensation Error rate equal to zero. AEC generates a maximum likelihood (ML) estimate of the hardware Error and employs it for Error Cancellation. AEC is applied to a voltage overscaled 45-tap, 45nm CMOS finite impulse response (FIR) filter employed in a EEG seizure detection system. AEC is shown to perfectly compensate for Errors in the main FIR block and its reduced precision replica when they make Errors at a rate of up to 73% and 98%, respectively. The AEC-based FIR is compared with an uncompensated architecture, and a fast architecture. AEC's Error compensation capability enables it to achieve a 31.5% (at same supply voltage) and 19.7% (at same energy) speed-up over the uncompensated architecture, and a 8. 9% speed-up over a fast architecture at the same energy consumption. At fd, k = 452.3 MHz, AEC results in a 27.7% and 12.4% energy savings over the uncompensated and fast architectures, respectively.
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Low-power filtering via adaptive Error-Cancellation
IEEE Transactions on Signal Processing, 2003Co-Authors: Lei Wang, N R ShanbhagAbstract:A low-power technique for digital filtering referred to as adaptive Error-Cancellation (AEC) is presented in this paper. The AEC technique falls under the general class of algorithmic noise-tolerance (ANT) techniques proposed earlier for combating transient/soft Errors. The proposed AEC technique exploits the correlation between the input and soft Errors to estimate and cancel out the latter. In this paper, we apply AEC along with voltage overscaling (VOS), where the voltage is scaled beyond the minimum (referred to as V/sub dd-crit/) necessary for correct operation. We employ the AEC technique in the context of a frequency-division multiplexed (FDM) communication system and demonstrate that up to 71% energy reduction can be achieved over present-day voltage-scaled systems.
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DAC - Reliable and energy-efficient digital signal processing
Proceedings of the 39th conference on Design automation - DAC '02, 2002Co-Authors: N R ShanbhagAbstract:This paper provides an overview of algorithmic noise-tolerance (ANT) for designing reliable and energy-efficient digital signal processing systems. Techniques such as prediction-based, Error Cancellation-based, and reduced precision redundancy based ANT are discussed. Average energy-savings range from 67% to 71% over conventional systems. Fluid IP core generators are proposed as a means of encapsulating the benefits of an ANT-based low-power design methodology. CAD issues resident in such a methodology are also discussed.
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Low-power signal processing via Error-Cancellation
2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528), 1Co-Authors: Lei Wang, N R ShanbhagAbstract:We present an algorithmic noise-tolerance (ANT) technique for designing low-power DSP systems. The proposed technique achieves substantial energy savings via voltage overscaling, whereby the supply voltage is scaled beyond the minimum supply voltage V/sub dd-crit/ at which the architecture operates correctly for a given throughput specification. The resulting input-dependent soft Errors are corrected via a low-complexity Error canceller and hence is referred to as adaptive Error-Cancellation. The trade-off between energy savings and algorithmic performance is illustrated by employing a reduced-order least mean square (LMS) algorithm to compensate for the design overhead. Simulation results in a 0.35 /spl mu/m CMOS technology demonstrate that the proposed technique achieves up to 73% energy savings in a multiuser communication scenario over present-day voltage-scaling, with a 3 dB algorithmic performance loss. Moreover, a 40% energy reduction is obtained over conventional DSP systems without algorithmic performance degradation.
Yongzhen Chen - One of the best experts on this subject based on the ideXlab platform.
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a 800 ms s 12 bit ringamp based sar assisted pipeline adc with gain Error Cancellation
International Symposium on Circuits and Systems, 2018Co-Authors: Yongzhen Chen, Yuefeng Cao, Junyan RenAbstract:A SAR assisted pipeline ADC with an inter-stage ring amplifier is an energy efficient structure. The ring amplifier is an alternative to an OTA for its low power consumption and large output swing. To improve the accuracy of the common-mode feedback circuit and speed up the settling of the ring amplifier, an improved bias-enhanced ring amplifier is proposed. Additionally, to alleviate the loss of the ring amplifier's DC gain in the nanoscale CMOS process and to migrate the dynamic offset caused by the non-ideal switches, a gain Error Cancellation method is introduced by adding a feedforward amplification path. Designed in a 1 V 28 nm CMOS process, two cascaded pipeline stages and two time-interleaved SAR sub-ADCs make up the ADC. In the post layout simulation that includes transient noise and other non-ideal factors, this 12-bit ADC achieves 60.9dB SNDR and 72dB SFDR at a Nyquist input and sampled at 800 MS/s without analog Cancellation, consuming 16.02mW. With gain Error Cancellation, SFDR is improved by more than 3dB.
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ISCAS - A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018Co-Authors: Yongzhen Chen, Yuefeng Cao, Junyan RenAbstract:A SAR assisted pipeline ADC with an inter-stage ring amplifier is an energy efficient structure. The ring amplifier is an alternative to an OTA for its low power consumption and large output swing. To improve the accuracy of the common-mode feedback circuit and speed up the settling of the ring amplifier, an improved bias-enhanced ring amplifier is proposed. Additionally, to alleviate the loss of the ring amplifier's DC gain in the nanoscale CMOS process and to migrate the dynamic offset caused by the non-ideal switches, a gain Error Cancellation method is introduced by adding a feedforward amplification path. Designed in a 1 V 28 nm CMOS process, two cascaded pipeline stages and two time-interleaved SAR sub-ADCs make up the ADC. In the post layout simulation that includes transient noise and other non-ideal factors, this 12-bit ADC achieves 60.9dB SNDR and 72dB SFDR at a Nyquist input and sampled at 800 MS/s without analog Cancellation, consuming 16.02mW. With gain Error Cancellation, SFDR is improved by more than 3dB.
Muhammad Ammirrul Atiqi Mohd Zainuri - One of the best experts on this subject based on the ideXlab platform.
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Photovoltaic Integrated Shunt Active Power Filter with Simpler ADALINE Algorithm for Current Harmonic Extraction
Energies, 2018Co-Authors: Muhammad Ammirrul Atiqi Mohd Zainuri, Mohd Amran Mohd Radzi, Norman Mariun, Azura Che Soh, Nasrudin Abd Rahim, Jiashen Teh, Ching-ming LaiAbstract:This manuscript presents a significant work in improving the current harmonics extraction algorithm and indirectly improving the injection current produced by a single-phase Photovoltaic Shunt Active Power Filter (PV SAPF). Improvement to the existing adaptive linear neuron (ADALINE) technique has been carried out, leading to the formation of a simpler ADALINE; it is expected to perform as fast as the current harmonics extraction algorithm. Further analysis on the DC link capacitor control algorithm, called “self-charging with step size Error Cancellation”, was also done to inspect the performance of the algorithm in a single-phase photovoltaic shunt active power filter system. Both algorithms, configured in single-phase PV SAPF, were simulated in MATLAB/Simulink (R2012b). A laboratory prototype was developed, and the algorithms were computed on a TMS320F28335 Digital Signal Processing (DSP) board for hardware implementation purposes. From the acquired results, the simpler ADALINE algorithm has effectively performed with lower total harmonic Distortion (THD) and outstanding compensation. The established algorithm of self-charging with step size Error Cancellation works well with single-phase PV SAPF and has shown less overshoot, a fast response time, and minimal energy losses.
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Photovoltaic shunt active power filter based on indirect self-charging with step size Error Cancellation and simplified adaptive linear neuron
2017Co-Authors: Muhammad Ammirrul Atiqi Mohd Zainuri, Muhammad Ammirrul AtiqiAbstract:Current harmonics is one of the main power quality problems which can be mitigated by using shunt active power filter (SAPF). Integrating SAPF with photovoltaic (PV), also known as PV SAPF, is among the best option as it provides alternative energy source to operate the SAPF rather than depending on energy from the grid supply and at the same time maintaining Total Harmonics Distortion (THD) below 5%. DC-link capacitor voltage control and harmonics extraction algorithms, are giving high impact to overall SAPF’s performance. In DC-link capacitor voltage control, the existing works on direct self-charging algorithm still have many drawbacks in terms of overshoot, undershoot and response time, especially during dynamic operation. Meanwhile, the existing harmonics extraction algorithm known as modified Widrow- Hoff adaptive linear neuron (ADALINE) algorithm, still has unnecessary features which unfortunately disturbs performance of the algorithm to extract harmonics accurately in both steady-state and dynamic operations. Therefore, this research work proposes design and development of single-phase PV SAPF with a new DC-link capacitor voltage control algorithm named as indirect self- charging with step size Error Cancellation, and a new harmonics extraction algorithm named as simplified ADALINE. In the indirect self-charging with step size Error Cancellation, a new technique has been introduced in operation of the self-charging algorithm, known later as indirect control technique. Meanwhile, the simplified ADALINE algorithm has been improved from its existing version by removing cosine component according to symmetrical theory of periodic signal, minimizing large average square Error by removing sum of elements, and by modifying weight updating technique leads to introduction of fundamental active current updating technique. In methodology, topology of PV SAPF was designed first, and followed by all control algorithms with special attention to both proposed algorithms. For comparison purpose, the existing DC-link capacitor voltage control and harmonics extraction algorithms were modeled too. Two nonlinear loads, which are inductive and capacitive, and PV source with different level of irradiances were used to test the PV SAPF by focusing on the performances of both proposed algorithms, under steady-state operation. The testing under dynamic operation covers change of nonlinear loads, on-off operations between PV and SAPF, and change of irradiance levels. Laboratory prototype was then developed and digital signal processor (DSP) TMS320F28335 was used to perform the computation of algorithms. Similar tests as in the simulation work were carried out in the laboratory. From both simulation and experimental results, PV SAPF with both proposed algorithms show better performances as compared to the existing algorithms. The indirect self-charging with step size Error Cancellation performs with high accuracy (99.96 to 100%), low overshoot and undershoot (0.13% to 1%), and fast response time (less than 0.5s). Reduction of energy losses between 36 J to 86 J has been achieved during various dynamic operations of the DC-link capacitor. Meanwhile, the simplified ADALINE performs with lower THD values between 1.5% to 3.24% and high percentages of source power reduction between 4.7% to 23.7% with different nonlinear loads and irradiance levels. In conclusion, PV SAPF with both proposed algorithms have successfully been developed and performed for better improvement of harmonics mitigation and renewable energy utilization.
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dc link capacitor voltage control for single phase shunt active power filter with step size Error Cancellation in self charging algorithm
Iet Power Electronics, 2016Co-Authors: Muhammad Ammirrul Atiqi Mohd Zainuri, Mohd Amran Mohd Radzi, Norman Mariun, N A RahimAbstract:This study presents an improved self-charging algorithm by introducing a new feature known as step size Error Cancellation for better performance of DC-link capacitor voltage control in single-phase shunt active power filter (SAPF). Previous works of self-charging algorithms were focused only for steady-state operation by using either proportional-integral (PI) or fuzzy logic control (FLC). However, in a certain operation of any power system, dynamic operation may also happen. Thus, by introducing step size Error Cancellation as an additional feature to the self-charging algorithm, both steady state and dynamic operations can be covered. For evaluation and comparison analysis, self-charging with PI and FLC algorithms have been developed too. All the algorithms were simulated in MATLAB-Simulink, respectively, together with the single-phase SAPF. For hardware implementation, the proposed algorithm was programmed in TMS320F28335 digital signal processing board. The other two conventional self-charging algorithms were also programmed for comparison purposes. From the results and analysis, the proposed self-charging with step size Error Cancellation shows the best performance with high accuracy, fast response time and less overshoot and undershoot. It performs well in both steady state and dynamic operations as compared with both previous self-charging techniques which only work well in steady-state operation.
Nam Ik Cho - One of the best experts on this subject based on the ideXlab platform.
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Low-Power Filtering Via Minimum Power Soft Error Cancellation
IEEE Transactions on Signal Processing, 2007Co-Authors: Jun Won Choi, Byonghyo Shim, Andrew C. Singer, Nam Ik ChoAbstract:In this paper, an energy-efficient estimation and detection problem is formulated for low-power digital filtering. Building on the soft digital signal processing technique proposed by Hegde and Shanbhag, which combines algorithmic noise tolerance and voltage scaling to reduce power, the proposed minimum power soft Error Cancellation (MP-SEC) technique detects, estimates, and corrects transient Errors that arise from voltage overscaling. These timing violation-induced Errors, called soft Errors, can be detected and corrected by exploiting the correlation structure induced by the filtering operation being protected, together with a reduced-precision replica of the protected operation. By exploiting a spacing property of soft Errors in certain architectures, MP-SEC can achieve up to 30% power savings with no signal-to-noise ratio (SNR) loss and up to 55% power savings with less than 1-dB SNR loss, according to the logic-level simulations performed for an example 25-tap frequency-selective filter.
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Low-Power Filtering via Minimum Power Soft Error Cancellation (MP-SEC)
2006Co-Authors: Jun Won Choi, Byonghyo Shim, Andrew C. Singer, Nam Ik ChoAbstract:In this paper, an energy-efficient estimation and detection problem is formulated for low-power digital filtering. Building on the soft digital signal processing technique proposed by Hegde et al., that combines algorithmic noise tolerance (ANT) and voltage scaling to reduce power, the proposed minimum power soft Error Cancellation (MP-SEC) technique detects, estimates and corrects transient Errors that arise from voltage over-scaling. These timing violation-induced Errors, called soft Errors, can be detected and corrected by exploiting the correlation structure induced by the filtering operation being protected, together with a reduced-precision replica of the protected operation. By exploiting a spacing property of soft Errors in certain architectures, MP-SEC can achieve up to 30% power savings with no SNR loss and up to 55% power savings with less 1 dB SNR loss, for an example 25-tap frequency-selective filter.
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ICASSP (4) - Low-Power Adaptive FIR Equalizer Via Soft Error Cancellation
2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings, 1Co-Authors: Jun Won Choi, Andrew C. Singer, Nam Ik ChoAbstract:In this paper, we present an adaptive FIR equalizer which reduces power dissipation by employing a new algorithmic Error correction technique. Building on the voltage over-scaling (VOS) technique, we formulate the statistical estimation of timing Errors that may be caused by VOS, called soft Errors to detect and cancel them at a system level. We derive a minimum variance unbiased estimator, and develop an adaptive and power-optimized algorithm for an adaptive equalizer. Up to 30% power savings are demonstrated with negligible performance loss for an example, 16-tap minimum mean square Error (MMSE) FIR equalizer.