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Hanho Lee - One of the best experts on this subject based on the ideXlab platform.

  • a high speed pipelined degree computationless modified Euclidean Algorithm architecture for reed solomon decoders
    IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2008
    Co-Authors: Seungbeom Lee, Hanho Lee
    Abstract:

    This paper presents a novel high-speed low-complexity pipelined degree-computationless modified Euclidean (pDCME) Algorithm architecture for high-speed RS decoders. The pDCME Algorithm allows elimination of the degree-computation so as to reduce hardware complexity and obtain high-speed processing. A high-speed RS decoder based on the pDCME Algorithm has been designed and implemented with 0.13-μm CMOS standard cell technology in a supply voltage of 1.1 V. The proposed RS decoder operates at a clock frequency of 660 MHz and has a throughput of 5.3 Gb/s. The proposed architecture requires approximately 15% fewer gate counts and a simpler control logic than architectures based on the popular modified Euclidean Algorithm.

  • high speed vlsi architecture for parallel reed solomon decoder
    International Symposium on Circuits and Systems, 2003
    Co-Authors: Hanho Lee
    Abstract:

    This paper presents high-speed parallel RS(255,239) decoder architecture using a modified Euclidean Algorithm for the high-speed fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber optic rates and outputs to be delivered at correspondingly high rates with minimum delay. Parallel processing architecture results in a speed-ups of as much as or more than 10 Gbits/s, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean Algorithm block. The parallel RS decoders have been designed and implemented with the 0.1 3-/spl mu/m CMOS standard cell technology in a supply voltage of 1.1V. It is suggested that a parallel RS decoder, which can keep up with optical transmission rates, i.e., 10 Gbits/s and beyond, could be implemented. The proposed channel=4 parallel RS decoder operates at a clock frequency of 770 MHz and has a throughput of 26.6 Gbits/s.

  • high speed vlsi architecture for parallel reed solomon decoder
    IEEE Transactions on Very Large Scale Integration Systems, 2003
    Co-Authors: Hanho Lee
    Abstract:

    This paper presents high-speed parallel Reed-Solomon (RS) (255,239) decoder architecture using modified Euclidean Algorithm for the high-speed multigigabit-per-second fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber-optic rates and outputs to be delivered at correspondingly high rates with minimum delay. A parallel processing architecture results in speed-ups of as much as or more than 10 Gb, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean Algorithm block. The parallel RS decoders have been designed and implemented with the 0.13-/spl mu/m CMOS standard cell technology in a supply voltage of 1.1 V. It is suggested that a parallel RS decoder, which can keep up with optical transmission rates, i.e., 10 Gb/s and beyond, could be implemented. The proposed channel = 4 parallel RS decoder operates at a clock frequency of 770 MHz and has a data processing rate of 26.6 Gb/s.

  • an area efficient Euclidean Algorithm block for reed solomon decoder
    IEEE Computer Society Annual Symposium on VLSI, 2003
    Co-Authors: Hanho Lee
    Abstract:

    This paper presents a new area-efficient architecture to implement the Euclidean Algorithm, which is frequently used in Reed-Solomon decoders. The RS (255,239) decoder using the Euclidean Algorithm has been implemented with 0.13 /spl mu/m CMOS technology with a supply voltage of 1.1 V. We investigate hardware complexity, clock frequency and data processing rate for this Euclidean Algorithm block. The results show that the total number of gates is about 44,700 and it has a data processing rate of 2.4 Gbits/s at a clock frequency of 300 MHz. As compared to the other RS decoders, it gains significant improvements in hardware complexity and latency.

  • modified Euclidean Algorithm block for high speed reed solomon decoder
    Electronics Letters, 2001
    Co-Authors: Hanho Lee
    Abstract:

    A new modified Euclidean (ME) Algorithm block for the high-speed Reed-Solomon (RS) decoder is presented. The RS decoder using the ME Algorithm has been implemented with standard 0.16 /spl mu/m CMOS cell technology with a supply voltage of 1.5 V. The results show that it operates at a clock frequency of 300 MHz and has a data processing rate of 2.4 Gbit/s.

Martin Bossert - One of the best experts on this subject based on the ideXlab platform.

Yunghsiang S Han - One of the best experts on this subject based on the ideXlab platform.

  • fft Algorithm for binary extension finite fields and its application to reed solomon codes
    IEEE Transactions on Information Theory, 2016
    Co-Authors: Sianjheng Lin, Tareq Y Alnaffouri, Yunghsiang S Han
    Abstract:

    Recently, a new polynomial basis over binary extension fields was proposed, such that the fast Fourier transform (FFT) over such fields can be computed in the complexity of order $\mathcal {O}(n\lg (n))$ , where $n$ is the number of points evaluated in FFT. In this paper, we reformulate this FFT Algorithm, such that it can be easier understood and be extended to develop frequency-domain decoding Algorithms for $(n=2^{m},k)$ systematic Reed–Solomon (RS) codes over $\mathbb {F}_{2^{m}},m\in \mathbb {Z}^{+}$ , with $n-k$ a power of two. First, the basis of syndrome polynomials is reformulated in the decoding procedure so that the new transforms can be applied to the decoding procedure. A fast extended Euclidean Algorithm is developed to determine the error locator polynomial. The computational complexity of the proposed decoding Algorithm is $\mathcal {O}(n\lg (n-k)+(n-k)\lg ^{2}(n-k))$ , improving upon the best currently available decoding complexity $\mathcal {O}(n\lg ^{2}(n)\lg \lg (n))$ , and reaching the best known complexity bound that was established by Justesen in 1976. However, Justesen’s approach is only for the codes over some specific fields, which can apply Cooley–Tukey FFTs. As revealed by the computer simulations, the proposed decoding Algorithm is 50 times faster than the conventional one for the $(2^{16},2^{15})$ RS code over $\mathbb {F}_{2^{16}}$ .

  • fft Algorithm for binary extension finite fields and its application to reed solomon codes
    arXiv: Information Theory, 2015
    Co-Authors: Sianjheng Lin, Tareq Y Alnaffouri, Yunghsiang S Han
    Abstract:

    Recently, a new polynomial basis over binary extension fields was proposed such that the fast Fourier transform (FFT) over such fields can be computed in the complexity of order $\mathcal{O}(n\lg(n))$, where $n$ is the number of points evaluated in FFT. In this work, we reformulate this FFT Algorithm such that it can be easier understood and be extended to develop frequency-domain decoding Algorithms for $(n=2^m,k)$ systematic Reed-Solomon~(RS) codes over $\mathbb{F}_{2^m},m\in \mathbb{Z}^+$, with $n-k$ a power of two. First, the basis of syndrome polynomials is reformulated in the decoding procedure so that the new transforms can be applied to the decoding procedure. A fast extended Euclidean Algorithm is developed to determine the error locator polynomial. The computational complexity of the proposed decoding Algorithm is $\mathcal{O}(n\lg(n-k)+(n-k)\lg^2(n-k))$, improving upon the best currently available decoding complexity $\mathcal{O}(n\lg^2(n)\lg\lg(n))$, and reaching the best known complexity bound that was established by Justesen in 1976. However, Justesen's approach is only for the codes over some specific fields, which can apply Cooley-Tucky FFTs. As revealed by the computer simulations, the proposed decoding Algorithm is $50$ times faster than the conventional one for the $(2^{16},2^{15})$ RS code over $\mathbb{F}_{2^{16}}$.

Chung-huang Yang - One of the best experts on this subject based on the ideXlab platform.

  • Modular Arithmetic: From Ancient India to Public-Key Cryptography
    2015
    Co-Authors: T. R. N. Rao, Chung-huang Yang
    Abstract:

    Abstract. We begin with an Algorithm from Aryabhatiya, for solving the indeterminate equation a·x + c = b·y of degree one (also known as Diophantine equation) and its extension to solve the system of two residues X mod mi = Xi (for i =1, 2). This contribution known as Aryabhatiya Algorithm (AA) is very profound in the sense that the problem of two congruences was solved with just one modular inverse operation and a modular reduction to a smaller modulus than the compound modulus. We extend AA to any set of t residues and is stated as Aryabhata Remainder Theorem (ART) and an iterative Algorithm is given to solve for t moduli mi (i=1, 2,…, t). The ART, which has much in common with Extended Euclidean Algorithm (EEA), Chinese Remainder Theorem (CRT) and Garner’s Algorithm (GA), is shown to have a complexity comparable or better than CRT and GA. Key words: Diophantine equation, Aryabhata, systems of congruences, modular arithmetic, residue number system, modular inverse

  • Aryabhata Remainder Theorem: Relevance to Public-Key Crypto-Algorithms
    Circuits Systems and Signal Processing, 2006
    Co-Authors: T. R. N. Rao, Chung-huang Yang
    Abstract:

    Public-key crypto-Algorithms are widely employed for authentication, signatures, secret-key generation and access control. The new range of public-key sizes for RSA and DSA has gone up to 1024 bits and beyond. The elliptic-curve key range is from 162 bits to 256 bits. Many varied software and hardware Algorithms are being developed for implementation for smart-card crypto-coprocessors and for public-key infrastructure. We begin with an Algorithm from Aryabhatiya for solving the indeterminate equation a · x + c = b · y of degree one (also known as the Diophantine equation) and its extension to solve the system of two residues X mod m_i = X_i (for i = 1,2). This contribution known as the Aryabhatiya Algorithm (AA) is very profound in the sense that the problem of two congruences was solved with just one modular inverse operation and a modular reduction to a smaller modulus than the compound modulus. We extend AA to any set of t residues, and this is stated as the Aryabhata remainder theorem (ART). An iterative Algorithm is also given to solve for t moduli m_i (i = 1, 2,... , t). The ART, which has much in common with the extended Euclidean Algorithm (EEA), Chinese remainder theorem (CRT) and Garner's Algorithm (GA), is shown to have a complexity comparable to or better than that of the CRT and GA.

  • ARYABHATA REMAINDER THEOREM: RELEVANCE TO
    2004
    Co-Authors: T. R. N. Rao, Chung-huang Yang
    Abstract:

    Abstract. Public-key crypto-Algorithms are widely employed for authentication, signatures, secret-key generation and access control. The new range of public-key sizes for RSA and DSA has gone up to 1024 bits and beyond. The elliptic-curve key range is from 162 bits to 256 bits. Many varied software and hardware Algorithms are being developed for implementation for smart-card crypto-coprocessors and for public-key infrastructure. We begin with an Algorithm from Aryabhatiya for solving the indeterminate equation a ·x +c = b · y of degree one (also known as the Diophantine equation) and its extension to solve the system of two residues X mod mi = Xi (for i = 1, 2). This contribution known as the Aryabhatiya Algorithm (AA) is very profound in the sense that the problem of two congruences was solved with just one modular inverse operation and a modular reduction to a smaller modulus than the compound modulus. We extend AA to any set of t residues, and this is stated as the Aryabhata remainder theorem (ART). An iterative Algorithm is also given to solve for t moduli mi (i = 1, 2,...,t). The ART, which has much in common with the extended Euclidean Algorithm (EEA), Chinese remainder theorem (CRT) and Garner’s Algorithm (GA), is shown to have a complexity comparable to or better than that of the CRT and GA

  • Relevance to public-key crypto-Algorithms
    2004
    Co-Authors: T. R. N. Rao, Chung-huang Yang, Crypto Lab
    Abstract:

    Abstract. Public-key crypto-Algorithms are widely employed for authentication, signatures, secret-key generation and access control. The new range of public-key sizes for RSA and DSA has gone up to 1024 bits and beyond. Elliptic-curve key range is from 162 bits to 256 bits. Many varied software and hardware Algorithms are being developed for implementation for smart-card crypto-coprocessors and for public-key infrastructure. We begin with an Algorithm from Aryabhatiya, for solving the indeterminate equation a·x + c = b·y of degree one (also known as Diophantine equation) and its extension to solve the system of two residues X mod m i = X i (for i =1, 2). This contribution known as Aryabhatiya Algorithm (AA) is very profound in the sense that the problem of two congruences was solved with just one modular inverse operation and a modular reduction to a smaller modulus than the compound modulus. We extend AA to any set of t residues and is stated as Aryabhata Remainder Theorem (ART) and an iterative Algorithm is given to solve for t moduli mi (i=1, 2,…, t). The ART, which has much in common with Extended Euclidean Algorithm (EEA), Chinese Remainder Theorem (CRT) and Garner’s Algorithm (GA), is shown to have a complexity comparable or better than CRT and GA. 1

Erkay Savas - One of the best experts on this subject based on the ideXlab platform.

  • low power elliptic curve cryptography using scaled modular arithmetic
    Lecture Notes in Computer Science, 2004
    Co-Authors: Erdinc Ozturk, Berk Sunar, Erkay Savas
    Abstract:

    We introduce new modulus scaling techniques for transforming a class of primes into special forms which enables efficient arithmetic. The scaling technique may be used to improve multiplication and inversion in finite fields. We present an efficient inversion Algorithm that utilizes the structure of scaled modulus. Our inversion Algorithm exhibits superior performance to the Euclidean Algorithm and lends itself to efficient hardware implementation due to its simplicity. Using the scaled modulus technique and our specialized inversion Algorithm we develop an elliptic curve processor architecture. The resulting architecture successfully utilizes redundant representation of elements in GF(p) and provides a low-power, high speed, and small footprint specialized elliptic curve implementation.