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B. G. Fernandes - One of the best experts on this subject based on the ideXlab platform.

  • Switching State Vector Selection Strategies for Paralleled Multilevel Current-Fed Inverter Under Unequal DC-Link Currents Condition
    IEEE Transactions on Power Electronics, 2015
    Co-Authors: Vishal Vekhande, Nimish Kothari, B. G. Fernandes
    Abstract:

    A paralleled multilevel Inverter topology consists of n three-phase three-level current-Fed Inverters (CFIs) connected in parallel on ac side. AC currents with (2n+1) levels can be generated utilizing redundant switching states when all three-level Inverters have equal dc-link currents. However, the multilevel space vector diagram gets modified, redundancy in the switching states is lost and the multilevel current pattern changes when the dc-link current of all Inverters is not the same. This introduces low-frequency harmonics in output current, thereby deteriorating total harmonic distortion (THD). The presence of low-frequency components in the output current could be avoided by selecting suitable switching state vectors and ensuring proper time sharing among these vectors. Two methods to select such switching state vectors are proposed in this paper. In the first method, a reference current space vector is realized using the nearest switching state vectors. However, this method results in low-frequency pulsation in dc-link voltage of each Inverter. In the second method, the switching state vectors are chosen to eliminate this low-frequency pulsation. Effectiveness of these methods is experimentally validated for a five-level CFI. Further, performance of these methods is compared based on efficiency, THD, and dc-link voltage ripple for various inequality ratios in dc-link currents.

  • ICIT - Multilevel operation of a PV Fed grid connected current Fed Inverter under equal and unequal DC link currents
    2015 IEEE International Conference on Industrial Technology (ICIT), 2015
    Co-Authors: Anandbabu Chakravarthula, T. Chakridhar Reddy, B. G. Fernandes
    Abstract:

    In this paper, space vector pulse width modulation control of a five-level current-Fed grid tied photovoltaic (PV) system is analyzed. This system comprises of two current-Fed Inverters (CFIs) connected in parallel on AC-side. Each CFI is energized from a PV array of equal power rating. Unequal DC-link currents are inevitable in the above system due to partial shading effects. Therefore, the state vectors in the space vector hexagon of the above system get deformed. Consequently, implementation of SVPWM is complex i.e., in terms of sector identification and nearest vector time calculation. To address these limitations, a new SVPWM technique is proposed for above mentioned system. In this approach, each CFI is modulated corresponding to its space vector hexagon. Further, switching sequence of one CFI is phase shifted by 180° compared to the other and vice-versa. As a result, this system generates five-levels in the output phase current with equal DC-link currents. In addition, predominant harmonic harmonic spectrum of the output phase current is double the switching frequency. This leads to reduces size of filter components. The proposed SVPWM technique is analyzed on a 9 kW system using MATLAB/Simulink for wide range of modulation index. A scaled down prototype is developed to validate the proposed SVPWM technique experimentally and results are presented.

  • Central seven-level current-Fed Inverter with module-integrated DC-DC converters for grid-connected PV plant
    2014 IEEE 40th Photovoltaic Specialist Conference PVSC 2014, 2014
    Co-Authors: Vishal Vekhande, B. G. Fernandes
    Abstract:

    This paper proposes a system of current-Fed converters for the integration of a large photovoltaic (PV) plant with a utility AC grid. The system comprises of a central seven-level current-Fed Inverter (CFI) and a large number of PV modules with module-integrated DC-DC converter. The seven-level CFI consists of three three-phase, three-level CFI units connected in parallel on the AC-side. Dual inductor current-Fed push-pull topology is used for DC-DC converters which inject continuous current into the DC-bus of the CFI units. Seven-level output current waveform is obtained using space vector modulation (SVM) technique when DC-bus currents are equal. However, mismatch in module characteristics and non-uniform insolation levels cause unequal DC-bus currents leading to distortion of the output current waveform. This limitation is addressed by appropriate selection of the switching state vectors while employing SVM technique. The performance of the proposed power converters system is studied using MATLAB/Simulink.

  • Central multilevel current-Fed Inverter with module integrated DC-DC converters for grid-connected PV plant
    2013 IEEE Energy Conversion Congress and Exposition, 2013
    Co-Authors: Vishal Vekhande, B. G. Fernandes
    Abstract:

    This paper proposes a system of current-Fed converters for the integration of a large photovoltaic (PV) plant with a utility ac grid. The system comprises a large number of PV modules with module integrated dc-dc converter. A dual inductor current-Fed push-pull topology is proposed for this purpose. To meet the THD requirement along with low switching losses a central multilevel current-Fed Inverter (CFI) is proposed. It comprises two three-phase three-level CFI units connected in parallel on the ac side. The dc-dc converters inject continuous current into the dc-bus of the CFI units. Five-level output current waveform is obtained using space vector modulation (SVM) technique when dc-bus currents are equal. However, mismatch in module characteristics and non-uniform insolation levels cause unequal dc-bus currents leading to distortion of the output current waveform. This limitation is addressed by appropriate selection of the switching state vectors while employing SVM technique. Two methods for selection of the switching state vectors are presented. The performance of a 100 kW PV plant utilizing the proposed power converters system is studied using MATLAB/Simulink.

  • Space vector modulation strategy for three-phase multilevel current-Fed Inverter with unequal DC-link currents
    2013 IEEE ECCE Asia Downunder, 2013
    Co-Authors: Vishal Vekhande, B. G. Fernandes
    Abstract:

    Three-phase multilevel current waveforms with (2n + 1) current levels can be generated by connecting n three-phase three-level current-Fed Inverters (CFI) in parallel. However, it is found that the multilevel space vector diagram gets distorted and redundancy in the switching states is lost when the dc-link current of all the Inverters is not the same. As a result, output current has low frequency harmonic components thereby deteriorating the THD. The presence of these low frequency components in the output currents can be avoided if specific switching state vectors are chosen and proper time sharing among these vectors is ensured while employing space vector modulation technique. Two methods to select suitable switching state vectors are proposed in this paper. In the first method, nearest switching state vectors are utilized to realize a reference current space vector. It is found that this method leads to reduced overall switching losses in the system. In the second method, the switching state vectors are chosen to eliminate low frequency pulsations in dc-link voltage of each Inverter. It is observed that the sector identification and duty cycle calculation tasks are simplified in the second method. A 5-level CFI is simulated using MATLAB/Simulink.

Vishal Vekhande - One of the best experts on this subject based on the ideXlab platform.

  • Switching State Vector Selection Strategies for Paralleled Multilevel Current-Fed Inverter Under Unequal DC-Link Currents Condition
    IEEE Transactions on Power Electronics, 2015
    Co-Authors: Vishal Vekhande, Nimish Kothari, B. G. Fernandes
    Abstract:

    A paralleled multilevel Inverter topology consists of n three-phase three-level current-Fed Inverters (CFIs) connected in parallel on ac side. AC currents with (2n+1) levels can be generated utilizing redundant switching states when all three-level Inverters have equal dc-link currents. However, the multilevel space vector diagram gets modified, redundancy in the switching states is lost and the multilevel current pattern changes when the dc-link current of all Inverters is not the same. This introduces low-frequency harmonics in output current, thereby deteriorating total harmonic distortion (THD). The presence of low-frequency components in the output current could be avoided by selecting suitable switching state vectors and ensuring proper time sharing among these vectors. Two methods to select such switching state vectors are proposed in this paper. In the first method, a reference current space vector is realized using the nearest switching state vectors. However, this method results in low-frequency pulsation in dc-link voltage of each Inverter. In the second method, the switching state vectors are chosen to eliminate this low-frequency pulsation. Effectiveness of these methods is experimentally validated for a five-level CFI. Further, performance of these methods is compared based on efficiency, THD, and dc-link voltage ripple for various inequality ratios in dc-link currents.

  • Central seven-level current-Fed Inverter with module-integrated DC-DC converters for grid-connected PV plant
    2014 IEEE 40th Photovoltaic Specialist Conference PVSC 2014, 2014
    Co-Authors: Vishal Vekhande, B. G. Fernandes
    Abstract:

    This paper proposes a system of current-Fed converters for the integration of a large photovoltaic (PV) plant with a utility AC grid. The system comprises of a central seven-level current-Fed Inverter (CFI) and a large number of PV modules with module-integrated DC-DC converter. The seven-level CFI consists of three three-phase, three-level CFI units connected in parallel on the AC-side. Dual inductor current-Fed push-pull topology is used for DC-DC converters which inject continuous current into the DC-bus of the CFI units. Seven-level output current waveform is obtained using space vector modulation (SVM) technique when DC-bus currents are equal. However, mismatch in module characteristics and non-uniform insolation levels cause unequal DC-bus currents leading to distortion of the output current waveform. This limitation is addressed by appropriate selection of the switching state vectors while employing SVM technique. The performance of the proposed power converters system is studied using MATLAB/Simulink.

  • Central multilevel current-Fed Inverter with module integrated DC-DC converters for grid-connected PV plant
    2013 IEEE Energy Conversion Congress and Exposition, 2013
    Co-Authors: Vishal Vekhande, B. G. Fernandes
    Abstract:

    This paper proposes a system of current-Fed converters for the integration of a large photovoltaic (PV) plant with a utility ac grid. The system comprises a large number of PV modules with module integrated dc-dc converter. A dual inductor current-Fed push-pull topology is proposed for this purpose. To meet the THD requirement along with low switching losses a central multilevel current-Fed Inverter (CFI) is proposed. It comprises two three-phase three-level CFI units connected in parallel on the ac side. The dc-dc converters inject continuous current into the dc-bus of the CFI units. Five-level output current waveform is obtained using space vector modulation (SVM) technique when dc-bus currents are equal. However, mismatch in module characteristics and non-uniform insolation levels cause unequal dc-bus currents leading to distortion of the output current waveform. This limitation is addressed by appropriate selection of the switching state vectors while employing SVM technique. Two methods for selection of the switching state vectors are presented. The performance of a 100 kW PV plant utilizing the proposed power converters system is studied using MATLAB/Simulink.

  • Space vector modulation strategy for three-phase multilevel current-Fed Inverter with unequal DC-link currents
    2013 IEEE ECCE Asia Downunder, 2013
    Co-Authors: Vishal Vekhande, B. G. Fernandes
    Abstract:

    Three-phase multilevel current waveforms with (2n + 1) current levels can be generated by connecting n three-phase three-level current-Fed Inverters (CFI) in parallel. However, it is found that the multilevel space vector diagram gets distorted and redundancy in the switching states is lost when the dc-link current of all the Inverters is not the same. As a result, output current has low frequency harmonic components thereby deteriorating the THD. The presence of these low frequency components in the output currents can be avoided if specific switching state vectors are chosen and proper time sharing among these vectors is ensured while employing space vector modulation technique. Two methods to select suitable switching state vectors are proposed in this paper. In the first method, nearest switching state vectors are utilized to realize a reference current space vector. It is found that this method leads to reduced overall switching losses in the system. In the second method, the switching state vectors are chosen to eliminate low frequency pulsations in dc-link voltage of each Inverter. It is observed that the sector identification and duty cycle calculation tasks are simplified in the second method. A 5-level CFI is simulated using MATLAB/Simulink.

Hamid A. Toliyat - One of the best experts on this subject based on the ideXlab platform.

Sangshin Kwak - One of the best experts on this subject based on the ideXlab platform.

Bimal K. Bose - One of the best experts on this subject based on the ideXlab platform.

  • A neural-network-based space vector PWM of a five-level voltage-Fed Inverter
    Conference Record of the 2004 IEEE Industry Applications Conference 2004. 39th IAS Annual Meeting., 1
    Co-Authors: N.p. Filho, João Onofre Pereira Pinto, Bimal K. Bose
    Abstract:

    The paper describes an artificial neural network (ANN) based space vector pulse width modulation (SVM) for a five-level voltage-Fed Inverter. Basically, it uses two multilayer perceptron (MLP) type neural networks. The first ANN uses the amplitude and angle of the reference voltage vector to determine the nearest three vectors (NTV) of the Inverter by identifying the triangle wherein the reference vector lies. The second ANN is used to calculate the duty cycles of the three space vectors. An erasable programmable logic device (EPLD) synthesizes the PWM waves. The main advantages of this approach are the fast and simple implementation of the highly complex SVM algorithm for multilevel Inverters without loosing precision compared to the conventional DSP-based SVM algorithm. Performance of the Inverter using the proposed ANN-based SVM has been investigated extensively, and the results are found to be excellent. The principle described in the paper can be easily extended to an Inverter with higher number of levels.

  • Expert system based automated design technique of a voltage-Fed Inverter for induction motor drive
    Conference Record of the 1992 IEEE Industry Applications Society Annual Meeting, 1
    Co-Authors: S.m. Chhaya, Bimal K. Bose
    Abstract:

    The authors describe expert-system-base automate design of a pulse width modulation (PWM) voltage Fed Inverter for an induction motor drive on the basis of design specifications provided by the user, who could be a skilled or a semiskilled designer. During a typical consultation with the expert system, the user undergoes an interactive dialogue session in simple English to supply the details of load condition, power supply, etc., to the expert system. The expert system then designs the converter system in detail and the solution is displayed on the screen. The program is developed with the help of an expert system shell named Personal Consultant Plus (PC PLUS). The present program can design Inverter systems for the range of machines of 1-50 HP using bipolar junction transistors or insulated-gate bipolar transistors, but can be expanded for higher power range using other power devices. The knowledge base of the program incorporates the domain expertise of a power electronics design engineer and the database contains the ratings of power semiconductor devices from a particular vendor. >

  • Base/gate drive suppression of inactive power devices of a voltage-Fed Inverter and precision synthesis of AC voltage and DC link current waves
    [Proceedings] IECON '90: 16th Annual Conference of IEEE Industrial Electronics Society, 1
    Co-Authors: R.p. Joshi, Bimal K. Bose
    Abstract:

    A control principle that suppresses the base/gate drive of inactive power semiconductor devices of a voltage-Fed Inverter that supplies lagging reactive load is described. The principle is utilized to fabricate precisely the Inverter output AC voltage waves from the information of DC link voltage, base/gate drive logic waves, and estimated drops across the conducting devices. The estimation of DC link current from the drive logic waves and AC phase currents is also described. A complete control circuit for base/gate drive suppression and precision estimation circuits for Inverter AC voltages and DC link currents were designed and tested using a commercial three-phase transistor Inverter induction motor drive. >