The Experts below are selected from a list of 303 Experts worldwide ranked by ideXlab platform

Koji Nuida - One of the best experts on this subject based on the ideXlab platform.

  • efficiency and accuracy improvements of secure Floating Point Addition over secret sharing
    International Workshop on Security, 2020
    Co-Authors: Kota Sasaki, Koji Nuida
    Abstract:

    In secure multiparty computation (MPC), Floating-Point numbers should be handled in many potential applications, but these are basically expensive. In particular, for MPC based on secret sharing (SS), the Floating-Point Addition takes many communication rounds though the Addition is the most fundamental operation. In this paper, we propose an SS-based two-party protocol for Floating-Point Addition with 13 rounds (for single/double precision numbers), which is much fewer than the milestone work of Aliasgari et al. in NDSS 2013 (34 and 36 rounds, respectively) and also fewer than the state of the art in the literature. Moreover, in contrast to the existing SS-based protocols which are all based on “roundTowardZero” rounding mode in the IEEE 754 standard, we propose another protocol with 15 rounds which is the first result realizing more accurate “roundTiesToEven” rounding mode. We also discuss possible applications of the latter protocol to secure Validated Numerics (a.k.a. Rigorous Computation) by implementing a simple example.

  • IWSEC - Efficiency and Accuracy Improvements of Secure Floating-Point Addition over Secret Sharing
    Advances in Information and Computer Security, 2020
    Co-Authors: Kota Sasaki, Koji Nuida
    Abstract:

    In secure multiparty computation (MPC), Floating-Point numbers should be handled in many potential applications, but these are basically expensive. In particular, for MPC based on secret sharing (SS), the Floating-Point Addition takes many communication rounds though the Addition is the most fundamental operation. In this paper, we propose an SS-based two-party protocol for Floating-Point Addition with 13 rounds (for single/double precision numbers), which is much fewer than the milestone work of Aliasgari et al. in NDSS 2013 (34 and 36 rounds, respectively) and also fewer than the state of the art in the literature. Moreover, in contrast to the existing SS-based protocols which are all based on “roundTowardZero” rounding mode in the IEEE 754 standard, we propose another protocol with 15 rounds which is the first result realizing more accurate “roundTiesToEven” rounding mode. We also discuss possible applications of the latter protocol to secure Validated Numerics (a.k.a. Rigorous Computation) by implementing a simple example.

P M Seidel - One of the best experts on this subject based on the ideXlab platform.

  • ICECS - Optimized Arithmetic Hardware Design based on Hierarchical Formal Verification
    2006 13th IEEE International Conference on Electronics Circuits and Systems, 2006
    Co-Authors: N. Kikkeri, P M Seidel
    Abstract:

    The formal verification of optimized arithmetic circuits imposes several challenges. Performance-optimized IEEE Floating-Point implementations can be particularly hard verification cases for their size and their irregularities, for the redundancy that is often used in the representations of intermediate values, and by the complex non-standard logic optimizations that are incorporated in the designs. We formally verify the highly optimized Even-Seidel rounding algorithm for IEEE Floating-Point multiplication and IEEE Floating-Point Addition which incorporates the use of rounding injections. Our verification efforts are based on the PVS theorem-prover. We structure the whole verification process in a hierarchical fashion where existing specifications and properties are re-used to ease the overall effort. We show the benefits of our hierarchical approach by verifying two variants of the algorithm for performance optimized IEEE Floating-Point multiplication and IEEE Floating-Point Addition.

  • high radix implementation of ieee Floating Point Addition
    Symposium on Computer Arithmetic, 2005
    Co-Authors: P M Seidel
    Abstract:

    We are proposing a micro-architecture for high-performance IEEE Floating-Point Addition that is based on a (non-redundant) high-radix representation of the Floating-Point operands. The main improvement of the proposed IEEE FP Addition implementation is achieved by avoiding the computation of full alignment and normalization shifts which impose major delays in conventional implementations of IEEE FP Addition. This reduction is achieved at the cost of wider operand interfaces and an increased complexity for IEEE compliant rounding. We present a detailed discussion of an IEEE FP adder implementation using the proposed high-radix format and explain the specific benefits and challenges of the design.

  • design of an on line ieee Floating Point Addition unit for fpgas
    Field-Programmable Custom Computing Machines, 2004
    Co-Authors: S D Krueger, P M Seidel
    Abstract:

    We present the design of an on-line IEEE Floating-Point (FP) adder. In on-line arithmetic a result is computed as a digit serial output stream from digit serial input streams. The result digits begin to be produced a short delay after the first input digits arrive and before all the input digits have been received. On-line arithmetic proceeds from the most significant digit first through the least significant digit. Performing on-line Addition on IEEE FP numbers imposes challenges beyond the challenges of conventional on-line arithmetic, including the task of normalization and IEEE rounding and its effect on the digits already output. The proposed implementations are very suitable for FPGAs, because the serial organization simplifies critical components of conventional FPGA IEEE FP Addition implementations: Large alignment and normalization shifters are avoided allowing for reduced interconnection complexities and reasonable latencies at low implementation cost. The proposed implementations are fully compliant with the IEEE FP standard.

  • Delay-optimized implementation of IEEE Floating-Point Addition
    IEEE Transactions on Computers, 2004
    Co-Authors: P M Seidel, Guy Even
    Abstract:

    We present an IEEE Floating-Point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE Standard. The FP-adder design achieves a low latency by combining various optimization techniques such as: a nonstandard separation into two paths, a simple rounding algorithm, unification of rounding cases for Addition and subtraction, sign-magnitude computation of a difference based on one's complement subtraction, compound adders, and fast circuits for approximate counting of leading zeros from borrow-save representation. We present technology-independent analysis and optimization of our implementation based on the Logical Effort hardware model and we determine optimal gate sizes and optimal buffer insertion. We estimate the delay of our optimized design at 30.6 FO4 delays for double precision operands (15.3 FO4 delays per stage between latches). We overview other IEEE FP Addition algorithms from the literature and compare these algorithms with our algorithm. We conclude that our algorithm has shorter latency (-13 percent) and cycle time (-22 percent) compared to the next fastest algorithm.

  • how many logic levels does Floating Point Addition require
    International Conference on Computer Design, 1998
    Co-Authors: P M Seidel, Guy Even
    Abstract:

    We present an algorithm for IEEE Floating-Point Addition. The latency of the Addition algorithm for double precision is roughly 24 logic levels, not including delays of latches between pipeline stages. The algorithm accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly rounded sum/difference in the format required by the IEEE Standard. The presentation of the algorithm is technology independent and can serve as basis for evaluation and comparison with other Floating-Point Addition algorithms.

R. Tolimieri - One of the best experts on this subject based on the ideXlab platform.

  • FFT algorithms for prime transform sizes and their implementations on VAX, IBM3090VF, and IBM RS/6000
    IEEE Transactions on Signal Processing, 1993
    Co-Authors: James W. Cooley, R. Tolimieri
    Abstract:

    Variants of the Winograd fast Fourier transform (FFT) algorithm for prime transform size that offer options as to operational counts and arithmetic balance are derived. Their implementations on VAX, IBM 3090 VF, and IBM RS/6000 are discussed. For processors that perform Floating-Point Addition, Floating-Point multiplication, and Floating-Point multiply-add with the same time delay, variants of the FFT algorithm have been designed such that all Floating-Point multiplications can be overlapped by using multiply-add. The use of a tensor product formulation, throughout, gives a means for producing variants of algorithms matching computer architectures. >

  • ICASSP - Variants of the Winograd multiplicative FFT algorithms and their implementation on IBM RS/6000
    [Proceedings] ICASSP 91: 1991 International Conference on Acoustics Speech and Signal Processing, 1991
    Co-Authors: James W. Cooley, R. Tolimieri
    Abstract:

    Variants of the Winograd (1976, 1980) multiplicative FFT (fast Fourier transform) algorithm for transform sizes of primes and product of primes are derived, which take advantage of a computer architecture with a multiply-add feature. For processors which perform Floating-Point Addition, Floating-Point multiplication, and the Floating-Point multiply-add in one computer clock cycle, FFT algorithms can be designed such that all the Floating-Point multiplications can be overlapped by using multiply-adds. Implementation of multiply-add algorithms on an IBM RS/6000 is discussed. The use of a tensor product formulation throughout gives a means for producing variants of algorithms matching computer architectures. >

Paolo Ienne - One of the best experts on this subject based on the ideXlab platform.

  • synthesis of Floating Point Addition clusters on fpgas using carry save arithmetic
    Field-Programmable Logic and Applications, 2010
    Co-Authors: Amit Verma, Ajay K Verma, Hadi Parandehafshar, Philip Brisk, Paolo Ienne
    Abstract:

    A new method to synthesize clusters of Floating-Point Addition operations on FPGAs is presented. Similar to Altera’s Floating-Point data path compiler, it performs normalization once, at the output of the cluster operation. All significands in the clustered operation are denormalized in parallel with respect to the largest exponent: a fixed-Point compressor tree then sums the aligned significands, followed by normalization and rounding. Compared to Altera’s Floating-Point datapath compiler, our method reduces the critical path delay by as much as 20%, and area by as much as 29% on Altera Stratix III FPGAs.

  • FPL - Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic
    2010 International Conference on Field Programmable Logic and Applications, 2010
    Co-Authors: Amit Verma, Ajay K Verma, Philip Brisk, Hadi Parandeh-afshar, Paolo Ienne
    Abstract:

    A new method to synthesize clusters of Floating-Point Addition operations on FPGAs is presented. Similar to Altera’s Floating-Point data path compiler, it performs normalization once, at the output of the cluster operation. All significands in the clustered operation are denormalized in parallel with respect to the largest exponent: a fixed-Point compressor tree then sums the aligned significands, followed by normalization and rounding. Compared to Altera’s Floating-Point datapath compiler, our method reduces the critical path delay by as much as 20%, and area by as much as 29% on Altera Stratix III FPGAs.

  • ASP-DAC - Hybrid LZA: a near optimal implementation of the leading zero anticipator
    2009 Asia and South Pacific Design Automation Conference, 2009
    Co-Authors: Amit Verma, Ajay K Verma, Philip Brisk, Paolo Ienne
    Abstract:

    The Leading Zero Anticipator (LZA) is one of the main components used in Floating Point Addition. It tends to be on the critical path, so it has attracted the attention of many researchers in the past. Most LZAs used today can be classified in two categories: exact and inexact. Inexact LZAs are normally preferred due to their shorter critical paths and reduced complexity; however, the inexact LZA requires an Additional correct stage. In this paper we present a new LZA architecture that combines ideas taken from prior exact and inexact LZAs. Our new LZA improves the delay of Floating Point Addition by 7--10% compared to state of art techniques as well as reduces hardware area in most cases. We also establish theoretical lower bounds on the delay of an LZA and we show that our LZA is very close to these bounds.

A. Lacroix - One of the best experts on this subject based on the ideXlab platform.