The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Dennis Sylvester - One of the best experts on this subject based on the ideXlab platform.
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a statistical approach for full chip Gate Oxide reliability analysis
International Conference on Computer Aided Design, 2008Co-Authors: Kaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis SylvesterAbstract:Gate Oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip Oxide reliability analysis assumes a uniform Oxide-thickness for all devices. In practice, however, Gate-Oxide thickness varies from die-to-die and within-die and as the precision of process control worsens an alternative reliability analysis approach is needed. In this work, we propose a statistical framework for chip level Gate Oxide reliability analysis while considering both die-to-die and within-die components of thickness variation. The thickness of each device is modeled as a distinct random variable and thus the full chip reliability estimation problem is defined on a huge sample space of several million devices. We observe that the full chip Oxide reliability is independent of the relative location of the individual devices. This enables us to transform the problem such that the resulting representation can be expressed in terms of only two distinct random variables. Using this transformation we present a computationally efficient and accurate approach for estimating the full chip reliability while considering spatial correlations of Gate-Oxide thickness. We show that, compared to Monte Carlo simulation, the proposed method incurs an error of only 1~6% while improving the runtime by around three orders.
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tradeoffs between Gate Oxide leakage and delay for dual t sub ox circuits
Design Automation Conference, 2004Co-Authors: Anup Kumar Sultania, Dennis Sylvester, Sachin S SapatnekarAbstract:Gate Oxide tunneling current (I Gate ) will become the dominant component of leakage in CMOS circuits as the physical Oxide thickness (T ox ) goes below 15AA. Increasing the value of T ox reduces the leakage at the expense of an increase in delay, and a practical tradeoff between delay and leakage can be achieved by assigning one of the two permissible T ox values to each transistor. In this paper, we propose an algorithm for dual T ox assignment to optimize the total leakage power under delay constraints, and generate a leakage/delay tradeoff curve. As compared to the case where all transistors are set to low T ox , our approach achieves an average leakage reduction of 83% under 100nm models.
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Gate Oxide leakage current analysis and reduction for vlsi circuits
IEEE Transactions on Very Large Scale Integration Systems, 2004Co-Authors: Dongwoo Lee, David Blaauw, Dennis SylvesterAbstract:In this paper we address the growing issue of Gate Oxide leakage current (I/sub Gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub Gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub Gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub Gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub Gate/. We find that for technologies with appreciable I/sub Gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.
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analysis and minimization techniques for total leakage considering Gate Oxide leakage
Design Automation Conference, 2003Co-Authors: Dongwoo Lee, David Blaauw, Wesley Kwong, Dennis SylvesterAbstract:In this paper we address the growing issue of Gate Oxide leakage current (IGate) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both IGate and subthreshold leakage (Isub). The interaction between Isub and IGate complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on table look-ups to quickly estimate the state-dependent total leakage current within 1% of SPICE. We then make several observations on the impact of IGate in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR vs. NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce IGate due to the dependence of Gate leakage on stack node voltages.
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analysis and minimization techniques for total leakage considering Gate Oxide leakage
Design Automation Conference, 2003Co-Authors: Dongwoo Lee, David Blaauw, Wesley Kwong, Dennis SylvesterAbstract:In this paper we address the growing issue of Gate Oxide leakage current (I/sub Gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub Gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub Gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on table look-ups to quickly estimate the state-dependent total leakage current within 1% of SPICE. We then make several observations on the impact of I/sub Gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR vs. NAND topologies. Based on these observations, we propose the use of pin recording as a means to reduce I/sub Gate/ due to the dependencies of Gate leakage on stack node voltages.
M Heyns - One of the best experts on this subject based on the ideXlab platform.
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soft breakdown of ultra thin Gate Oxide layers
IEEE Transactions on Electron Devices, 1996Co-Authors: M Depas, Tanya Nigam, M HeynsAbstract:The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a Gate dielectric in poly-Si Gate capacitors is investiGated. The ultra-thin Gate Oxide reliability was determined using tunnel current injection stressing measurements. A soft breakdown mechanism is demonstrated for these ultra-thin Gate Oxide layers. The soft breakdown phenomenon corresponds with an anomalous increase of the stress induced leakage current and the occurrence of fluctuations in the current. The soft breakdown phenomenon is explained by the decrease of the applied power during the stressing for thinner Oxides so that thermal effects are avoided during the breakdown of the ultra-thin Oxide capacitor. It is proposed that multiple tunnelling via generated electron traps in the ultra-thin Gate Oxide layer is the physical mechanism of the electron transport after soft breakdown. The statistical distributions of the charge to dielectric breakdown and to soft breakdown for a constant current stress of the ultra-thin Oxides are compared. It is shown that for accurate ultra-thin Gate Oxide reliability measurements it is necessary to take the soft breakdown phenomenon into account.
Heungjae Cho - One of the best experts on this subject based on the ideXlab platform.
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Gate Oxide reliability characterization of tungsten polymetal Gate with low contact resistive wsix wn diffusion barrier in memory devices
Japanese Journal of Applied Physics, 2007Co-Authors: Min Gyu Sung, Kwanyong Lim, Heungjae Cho, Seung Ryong Lee, Seaug Jang, Yong Soo Kim, Taeyoon Kim, Hongseon Yang, Jachun Ku, Jinwoong KimAbstract:Gate Oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) Gate stack were investiGated in detail. The insertion of a thin WSix layer in a tungsten poly Gate stack could effectively relieve the mechanical stress of a Gate hardmask nitride film during a post thermal process, which contributes to better Gate Oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si–N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSix/poly Gate stack could be a promising candidate for a future W poly Gate that shows reliable high-speed characteristics in dynamic random access memory applications.
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impact of thin wsix insertion in tungsten polymetal Gate on Gate Oxide reliability and Gate contact resistance
International Reliability Physics Symposium, 2006Co-Authors: Min Sung, Kwanyong Lim, Heungjae Cho, Seung Ryong Lee, Seaug Jang, Hongseon Yang, Kwangok Kim, Nohjung Kwak, Hyunchul Sohn, Jin KimAbstract:By inserting thin WSix layer in tungsten poly Gate stack we can effectively relieve the mechanical stress of Gate hard mask nitride film, which contributes to the better Gate Oxide reliability and stress- immunity of trasistor. This insertion also could prevent the formation of Si-N dielectric layer atop poly-Si, which could lower the contact resistance between poly and tungsten effectively.
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impact of atomic layer deposited tin on the Gate Oxide quality of w tin sio2 si metal Oxide semiconductor structures
Applied Physics Letters, 2002Co-Authors: Daegyu Park, Kwanyong Lim, Heungjae Cho, Taeho Cha, Inseok Yeo, Jaesung Roh, Jinwon ParkAbstract:We demonstrate the impact of atomic-layer-deposited TiN Gate on the characteristics of W/TiN/SiO2/p-Si metal–Oxide–semiconductor (MOS) systems. Damage-free Gate Oxide quality was attained with atomic-layer-deposition (ALD)–TiN as manifested by an excellent interface trap density (Dit) as low as ∼4×1010 eV−1 cm−2 near the Si midgap. ALD–TiN improved the Dit level of MOS systems on both thin SiO2 and high-permittivity (high-k) Gate dielectrics. The leakage current of a MOS capacitor Gated with ALD–TiN is remarkably lower than that with sputter-deposited TiN and poly-Si Gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving Gate Oxide reliability, paving a way for the direct metal Gate process.
Kwanyong Lim - One of the best experts on this subject based on the ideXlab platform.
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Gate Oxide reliability characterization of tungsten polymetal Gate with low contact resistive wsix wn diffusion barrier in memory devices
Japanese Journal of Applied Physics, 2007Co-Authors: Min Gyu Sung, Kwanyong Lim, Heungjae Cho, Seung Ryong Lee, Seaug Jang, Yong Soo Kim, Taeyoon Kim, Hongseon Yang, Jachun Ku, Jinwoong KimAbstract:Gate Oxide reliability characteristics using different diffusion barrier metals for a tungsten polycrystalline silicon (poly-Si) Gate stack were investiGated in detail. The insertion of a thin WSix layer in a tungsten poly Gate stack could effectively relieve the mechanical stress of a Gate hardmask nitride film during a post thermal process, which contributes to better Gate Oxide reliability and the stress-immunity of the transistor. This insertion could also prevent the formation of a Si–N inter-dielectric layer, which could lower the contact resistance between poly and tungsten effectively. A W/WN/WSix/poly Gate stack could be a promising candidate for a future W poly Gate that shows reliable high-speed characteristics in dynamic random access memory applications.
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impact of thin wsix insertion in tungsten polymetal Gate on Gate Oxide reliability and Gate contact resistance
International Reliability Physics Symposium, 2006Co-Authors: Min Sung, Kwanyong Lim, Heungjae Cho, Seung Ryong Lee, Seaug Jang, Hongseon Yang, Kwangok Kim, Nohjung Kwak, Hyunchul Sohn, Jin KimAbstract:By inserting thin WSix layer in tungsten poly Gate stack we can effectively relieve the mechanical stress of Gate hard mask nitride film, which contributes to the better Gate Oxide reliability and stress- immunity of trasistor. This insertion also could prevent the formation of Si-N dielectric layer atop poly-Si, which could lower the contact resistance between poly and tungsten effectively.
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impact of atomic layer deposited tin on the Gate Oxide quality of w tin sio2 si metal Oxide semiconductor structures
Applied Physics Letters, 2002Co-Authors: Daegyu Park, Kwanyong Lim, Heungjae Cho, Taeho Cha, Inseok Yeo, Jaesung Roh, Jinwon ParkAbstract:We demonstrate the impact of atomic-layer-deposited TiN Gate on the characteristics of W/TiN/SiO2/p-Si metal–Oxide–semiconductor (MOS) systems. Damage-free Gate Oxide quality was attained with atomic-layer-deposition (ALD)–TiN as manifested by an excellent interface trap density (Dit) as low as ∼4×1010 eV−1 cm−2 near the Si midgap. ALD–TiN improved the Dit level of MOS systems on both thin SiO2 and high-permittivity (high-k) Gate dielectrics. The leakage current of a MOS capacitor Gated with ALD–TiN is remarkably lower than that with sputter-deposited TiN and poly-Si Gate at the similar capacitance equivalent thickness (CET). Less chlorine content in ALD–TiN films appears to be pivotal in minimizing the CET increase against postmetal anneal and improving Gate Oxide reliability, paving a way for the direct metal Gate process.
Wenchin Lee - One of the best experts on this subject based on the ideXlab platform.
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modeling cmos tunneling currents through ultrathin Gate Oxide due to conduction and valence band electron and hole tunneling
IEEE Transactions on Electron Devices, 2001Co-Authors: Wenchin LeeAbstract:A semi-empirical model is proposed to quantify the tunneling currents through ultrathin Gate Oxides (1-3.6 nm). As a multiplier to a simple analytical model, a correction function is introduced to achieve universal applicability to all different combinations of bias polarities (inversion and accumulation), Gate materials (N/sup +/, P/sup +/, Si, SiGe) and tunneling processes. Each coefficient of the correction function is given a physical meaning and determined by empirical fitting. This new model can accurately predict all the current components that can be observed: electron tunneling from the conduction band (ECB), electron tunneling from the valence band (EVB), and hole tunneling from the valence hand (HVB) in dual-Gate poly-Si/sub 1-x/Ge/sub x/-Gated (x=0 or 0.25) CMOS devices for various Gate Oxide thicknesses. In addition, this model ran also be employed to determine the physical Oxide thickness from I-V data with high sensitivity. It is particularly sensitive in the very-thin-Oxide regime, where C-V extraction happens to be difficult or impossible (because of the presence of the large tunneling current).