The Experts below are selected from a list of 687 Experts worldwide ranked by ideXlab platform

Franz T. Geyling - One of the best experts on this subject based on the ideXlab platform.

  • Global Planarization of spun‐on thin films by reflow
    Applied Physics Letters, 1991
    Co-Authors: David E. Bornside, Robert A. Brown, Sanjiv Mittal, Franz T. Geyling
    Abstract:

    The leveling of a thin‐liquid film on a substrate having a mesa‐like feature is analyzed by finite element analysis and lubrication theory applied to the free‐surface viscous flow problem. The height of the mesa is on the order of 1 μm and has a width on the order of 100 μm; the thin‐liquid film is initially conformal to the substrate and has a thickness on the order of 1 μm. Capillarity is found to be the primary driving force for flow. The predicted leveling times from the numerical simulations compare favorably with an analytical solution developed from lubrication theory for the leveling of a thin film on a smooth substrate.

  • Global Planarization of spun on thin films by reflow
    Applied Physics Letters, 1991
    Co-Authors: David E. Bornside, Robert A. Brown, Sanjiv Mittal, Franz T. Geyling
    Abstract:

    The leveling of a thin‐liquid film on a substrate having a mesa‐like feature is analyzed by finite element analysis and lubrication theory applied to the free‐surface viscous flow problem. The height of the mesa is on the order of 1 μm and has a width on the order of 100 μm; the thin‐liquid film is initially conformal to the substrate and has a thickness on the order of 1 μm. Capillarity is found to be the primary driving force for flow. The predicted leveling times from the numerical simulations compare favorably with an analytical solution developed from lubrication theory for the leveling of a thin film on a smooth substrate.

Joseph P. Ellul - One of the best experts on this subject based on the ideXlab platform.

  • A One‐Step Shallow Trench Global Planarization Process Using Chemical Mechanical Polishing
    Journal of The Electrochemical Society, 1997
    Co-Authors: John M. Boyd, Joseph P. Ellul
    Abstract:

    The use of chemical-mechanical polishing (CMP) as a Planarization technique in VLSI process technology is increasing rapidly. However, many of the planarizing applications are directed toward interconnect dielectric Planarization for triple-level metal (TLM) and quadruple-level metal (QLM) schemes. Interest in CMP as a tool for use in shallow trench isolation is much more limited because of the dishing effect in wide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss the status of our Planarization technique, aimed at the development of a viable shallow trench isolation process for a CMOS technology. We discuss the initial effort which optimizes the planarizing characteristics of our polish process as a function of feature geometry, nitride overcoat, and nitride polish stop. It is shown that large and small features on a variety of mask layouts are planarized simultaneously without dishing. Small features are planarized quickly and remain protected by a nitride polish stop; larger features planarize more slowly and end on the nitride polish stop as well.

  • a one step shallow trench Global Planarization process using chemical mechanical polishing
    Journal of The Electrochemical Society, 1997
    Co-Authors: John M. Boyd, Joseph P. Ellul
    Abstract:

    The use of chemical-mechanical polishing (CMP) as a Planarization technique in VLSI process technology is increasing rapidly. However, many of the planarizing applications are directed toward interconnect dielectric Planarization for triple-level metal (TLM) and quadruple-level metal (QLM) schemes. Interest in CMP as a tool for use in shallow trench isolation is much more limited because of the dishing effect in wide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss the status of our Planarization technique, aimed at the development of a viable shallow trench isolation process for a CMOS technology. We discuss the initial effort which optimizes the planarizing characteristics of our polish process as a function of feature geometry, nitride overcoat, and nitride polish stop. It is shown that large and small features on a variety of mask layouts are planarized simultaneously without dishing. Small features are planarized quickly and remain protected by a nitride polish stop; larger features planarize more slowly and end on the nitride polish stop as well.

  • Near‐Global Planarization of Oxide‐Filled Shallow Trenches Using Chemical Mechanical Polishing
    Journal of The Electrochemical Society, 1996
    Co-Authors: John M. Boyd, Joseph P. Ellul
    Abstract:

    The use of chemical mechanical polishing (CMP) is rapidly increasing as a Planarization technique in very large scale integrated process technology. Many of the planarizing applications have been directed toward interconnect dielectric Planarization of triple level metal and quadruple level metal schemes. Interest in CMP as a tool for use in Planarization of oxide-filled shallow trenches is now increasing. Isolation planarity with the silicon surface is required for achieving maximum linewidth control during subsequent silicon gate processing. Increased planarity also helps reduce the amount of overetch required during the polysilicon definition step especially that is required to clear minimum poly-to-poly spaces. Reactive ion etching overetch can contribute to junction leakage and critical dimension tolerance degradation. The utilization of CMP has been limited because of the dishing effect in wide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss our shallow trench Planarization technique, using chemical mechanical polishing alone. Dishing was reduced to less than 10 nm across 6 mm wide field regions. Large and small features were planarized simultaneously.

  • near Global Planarization of oxide filled shallow trenches using chemical mechanical polishing
    Journal of The Electrochemical Society, 1996
    Co-Authors: John M. Boyd, Joseph P. Ellul
    Abstract:

    The use of chemical mechanical polishing (CMP) is rapidly increasing as a Planarization technique in very large scale integrated process technology. Many of the planarizing applications have been directed toward interconnect dielectric Planarization of triple level metal and quadruple level metal schemes. Interest in CMP as a tool for use in Planarization of oxide-filled shallow trenches is now increasing. Isolation planarity with the silicon surface is required for achieving maximum linewidth control during subsequent silicon gate processing. Increased planarity also helps reduce the amount of overetch required during the polysilicon definition step especially that is required to clear minimum poly-to-poly spaces. Reactive ion etching overetch can contribute to junction leakage and critical dimension tolerance degradation. The utilization of CMP has been limited because of the dishing effect in wide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss our shallow trench Planarization technique, using chemical mechanical polishing alone. Dishing was reduced to less than 10 nm across 6 mm wide field regions. Large and small features were planarized simultaneously.

David E. Bornside - One of the best experts on this subject based on the ideXlab platform.

  • Global Planarization of spun‐on thin films by reflow
    Applied Physics Letters, 1991
    Co-Authors: David E. Bornside, Robert A. Brown, Sanjiv Mittal, Franz T. Geyling
    Abstract:

    The leveling of a thin‐liquid film on a substrate having a mesa‐like feature is analyzed by finite element analysis and lubrication theory applied to the free‐surface viscous flow problem. The height of the mesa is on the order of 1 μm and has a width on the order of 100 μm; the thin‐liquid film is initially conformal to the substrate and has a thickness on the order of 1 μm. Capillarity is found to be the primary driving force for flow. The predicted leveling times from the numerical simulations compare favorably with an analytical solution developed from lubrication theory for the leveling of a thin film on a smooth substrate.

  • Global Planarization of spun on thin films by reflow
    Applied Physics Letters, 1991
    Co-Authors: David E. Bornside, Robert A. Brown, Sanjiv Mittal, Franz T. Geyling
    Abstract:

    The leveling of a thin‐liquid film on a substrate having a mesa‐like feature is analyzed by finite element analysis and lubrication theory applied to the free‐surface viscous flow problem. The height of the mesa is on the order of 1 μm and has a width on the order of 100 μm; the thin‐liquid film is initially conformal to the substrate and has a thickness on the order of 1 μm. Capillarity is found to be the primary driving force for flow. The predicted leveling times from the numerical simulations compare favorably with an analytical solution developed from lubrication theory for the leveling of a thin film on a smooth substrate.

Kee Soo Nam - One of the best experts on this subject based on the ideXlab platform.

  • Trench formation and filling technique for dielectric isolation of plasma display panel driver integrated circuits
    Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2000
    Co-Authors: Sang-gi Kim, Jongdae Kim, Jin Gun Koo, Kee Soo Nam, Kyoung-ik Cho, In-ho Bae
    Abstract:

    Trench etching and filling technique for the isolation between the control (low voltage) and the power (high voltage) region in power integrated circuits was investigated. This technique consists of a deep trench formation (8.0 μm) with positive etching using 45% He–O2 of the HBr and SiF4 chemistries followed by filling and Global Planarization with the chemical mechanical polishing technique. The novel trench etching technique provides better surface quality of 3.1 A roughness measured with atomic force microscopy. The filling and Global Planarization results in lower leakage current less than 1 nA at the supplying voltage of 400 V.

  • A novel trench formation and Planarization technique using positive etching and CMP for smart power ICs
    Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212), 1
    Co-Authors: Sungdo Kim, Jin Gun Koo, Jun-youn Kim, J.-w. Lee, Kee Soo Nam
    Abstract:

    A new trench isolation technique has been demonstrated which can be used to make high voltage integrated circuits with trench isolation. The technique consists of positive etching using HBr and SiF/sub 4/ chemistries with 45% He-O/sub 2/ additives and Global Planarization after trench refill techniques using chemical-mechanical polishing (CMP). The novel technique provides better surface quality of 3.1 /spl Aring/ RMS roughness as measured by AFM, better CMP uniformity of less than 3%, and better leakage characteristics of less than 1 nA at 400 V.

John M. Boyd - One of the best experts on this subject based on the ideXlab platform.

  • A One‐Step Shallow Trench Global Planarization Process Using Chemical Mechanical Polishing
    Journal of The Electrochemical Society, 1997
    Co-Authors: John M. Boyd, Joseph P. Ellul
    Abstract:

    The use of chemical-mechanical polishing (CMP) as a Planarization technique in VLSI process technology is increasing rapidly. However, many of the planarizing applications are directed toward interconnect dielectric Planarization for triple-level metal (TLM) and quadruple-level metal (QLM) schemes. Interest in CMP as a tool for use in shallow trench isolation is much more limited because of the dishing effect in wide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss the status of our Planarization technique, aimed at the development of a viable shallow trench isolation process for a CMOS technology. We discuss the initial effort which optimizes the planarizing characteristics of our polish process as a function of feature geometry, nitride overcoat, and nitride polish stop. It is shown that large and small features on a variety of mask layouts are planarized simultaneously without dishing. Small features are planarized quickly and remain protected by a nitride polish stop; larger features planarize more slowly and end on the nitride polish stop as well.

  • a one step shallow trench Global Planarization process using chemical mechanical polishing
    Journal of The Electrochemical Society, 1997
    Co-Authors: John M. Boyd, Joseph P. Ellul
    Abstract:

    The use of chemical-mechanical polishing (CMP) as a Planarization technique in VLSI process technology is increasing rapidly. However, many of the planarizing applications are directed toward interconnect dielectric Planarization for triple-level metal (TLM) and quadruple-level metal (QLM) schemes. Interest in CMP as a tool for use in shallow trench isolation is much more limited because of the dishing effect in wide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss the status of our Planarization technique, aimed at the development of a viable shallow trench isolation process for a CMOS technology. We discuss the initial effort which optimizes the planarizing characteristics of our polish process as a function of feature geometry, nitride overcoat, and nitride polish stop. It is shown that large and small features on a variety of mask layouts are planarized simultaneously without dishing. Small features are planarized quickly and remain protected by a nitride polish stop; larger features planarize more slowly and end on the nitride polish stop as well.

  • Near‐Global Planarization of Oxide‐Filled Shallow Trenches Using Chemical Mechanical Polishing
    Journal of The Electrochemical Society, 1996
    Co-Authors: John M. Boyd, Joseph P. Ellul
    Abstract:

    The use of chemical mechanical polishing (CMP) is rapidly increasing as a Planarization technique in very large scale integrated process technology. Many of the planarizing applications have been directed toward interconnect dielectric Planarization of triple level metal and quadruple level metal schemes. Interest in CMP as a tool for use in Planarization of oxide-filled shallow trenches is now increasing. Isolation planarity with the silicon surface is required for achieving maximum linewidth control during subsequent silicon gate processing. Increased planarity also helps reduce the amount of overetch required during the polysilicon definition step especially that is required to clear minimum poly-to-poly spaces. Reactive ion etching overetch can contribute to junction leakage and critical dimension tolerance degradation. The utilization of CMP has been limited because of the dishing effect in wide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss our shallow trench Planarization technique, using chemical mechanical polishing alone. Dishing was reduced to less than 10 nm across 6 mm wide field regions. Large and small features were planarized simultaneously.

  • near Global Planarization of oxide filled shallow trenches using chemical mechanical polishing
    Journal of The Electrochemical Society, 1996
    Co-Authors: John M. Boyd, Joseph P. Ellul
    Abstract:

    The use of chemical mechanical polishing (CMP) is rapidly increasing as a Planarization technique in very large scale integrated process technology. Many of the planarizing applications have been directed toward interconnect dielectric Planarization of triple level metal and quadruple level metal schemes. Interest in CMP as a tool for use in Planarization of oxide-filled shallow trenches is now increasing. Isolation planarity with the silicon surface is required for achieving maximum linewidth control during subsequent silicon gate processing. Increased planarity also helps reduce the amount of overetch required during the polysilicon definition step especially that is required to clear minimum poly-to-poly spaces. Reactive ion etching overetch can contribute to junction leakage and critical dimension tolerance degradation. The utilization of CMP has been limited because of the dishing effect in wide field regions, as well as the difficulty of planarizing large and small features simultaneously. In this work, we discuss our shallow trench Planarization technique, using chemical mechanical polishing alone. Dishing was reduced to less than 10 nm across 6 mm wide field regions. Large and small features were planarized simultaneously.