The Experts below are selected from a list of 1401 Experts worldwide ranked by ideXlab platform
Clement Merckling - One of the best experts on this subject based on the ideXlab platform.
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heteroepitaxy of inp on si 001 by selective area metal organic vapor phase epitaxy in sub 50 nm width Trenches the role of the nucleation layer and the recess engineering
Journal of Applied Physics, 2014Co-Authors: Clement Merckling, Aaron Thean, Nadine Collaert, Niamh Waldron, Sijia Jiang, W Guo, Matty Caymax, E Vancoille, K Barla, Marc HeynsAbstract:This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in Shallow Trench Isolation Trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.
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selective area growth of inp in Shallow Trench Isolation on large scale si 001 wafer using defect confinement technique
Journal of Applied Physics, 2013Co-Authors: Clement Merckling, Niamh Waldron, Sijia Jiang, W Guo, O Richard, Bastien Douhard, Alain Moussa, D Vanhaeren, H Bender, Nadine CollaertAbstract:Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the Trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the Trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III–V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III–V virtual substrates on large-scale Si substrates.
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towards the monolithic integration of iii v compound semiconductors on si selective area growth in high aspect ratio structures vs strain relaxed buffer mediated epitaxy
Compound Semiconductor Integrated Circuit Symposium, 2012Co-Authors: M Cantoro, Clement Merckling, Niamh Waldron, Sijia Jiang, W Guo, Bastien Douhard, Alain Moussa, H Bender, Wilfried Vandervorst, M HeynsAbstract:We report two approaches to integrate high quality III-V templates by epitaxial growth with low defectivity on Si wafers. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagation from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.
Nadine Collaert - One of the best experts on this subject based on the ideXlab platform.
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Impact of the low temperature operation on long channel strained Ge pFinFETs fabricated with STI first and last processes
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016Co-Authors: Alberto Vinícius De Oliveira, Jérôme Mitard, Liesbeth Witters, Joao Antonio Martino, Paula Ghedini Der Agopian, Aaron Thean, Nadine Collaert, Eddy Simoen, Cor ClaeysAbstract:One of future device candidates for the Si platform integration, the Ge pFinFET, is evaluated for two different Shallow-Trench-Isolation (STI) processes at low temperature operation. The effective mobility around 700 cm2/Vs at 77 K is reported for both STI processes, as a result of the compressive strain in the channel. Regarding the OFF-state region, it is found that the substrate current plays an important role at room temperature and for long channels. It decreases up to three orders of magnitude from room temperature down to 200 K, as long as the p-n junction reverse current from the drain to bulk dominates the substrate current.
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heteroepitaxy of inp on si 001 by selective area metal organic vapor phase epitaxy in sub 50 nm width Trenches the role of the nucleation layer and the recess engineering
Journal of Applied Physics, 2014Co-Authors: Clement Merckling, Aaron Thean, Nadine Collaert, Niamh Waldron, Sijia Jiang, W Guo, Matty Caymax, E Vancoille, K Barla, Marc HeynsAbstract:This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in Shallow Trench Isolation Trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.
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selective area growth of inp in Shallow Trench Isolation on large scale si 001 wafer using defect confinement technique
Journal of Applied Physics, 2013Co-Authors: Clement Merckling, Niamh Waldron, Sijia Jiang, W Guo, O Richard, Bastien Douhard, Alain Moussa, D Vanhaeren, H Bender, Nadine CollaertAbstract:Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the Trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the Trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III–V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III–V virtual substrates on large-scale Si substrates.
W Guo - One of the best experts on this subject based on the ideXlab platform.
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heteroepitaxy of inp on si 001 by selective area metal organic vapor phase epitaxy in sub 50 nm width Trenches the role of the nucleation layer and the recess engineering
Journal of Applied Physics, 2014Co-Authors: Clement Merckling, Aaron Thean, Nadine Collaert, Niamh Waldron, Sijia Jiang, W Guo, Matty Caymax, E Vancoille, K Barla, Marc HeynsAbstract:This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in Shallow Trench Isolation Trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.
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selective area growth of inp in Shallow Trench Isolation on large scale si 001 wafer using defect confinement technique
Journal of Applied Physics, 2013Co-Authors: Clement Merckling, Niamh Waldron, Sijia Jiang, W Guo, O Richard, Bastien Douhard, Alain Moussa, D Vanhaeren, H Bender, Nadine CollaertAbstract:Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the Trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the Trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III–V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III–V virtual substrates on large-scale Si substrates.
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towards the monolithic integration of iii v compound semiconductors on si selective area growth in high aspect ratio structures vs strain relaxed buffer mediated epitaxy
Compound Semiconductor Integrated Circuit Symposium, 2012Co-Authors: M Cantoro, Clement Merckling, Niamh Waldron, Sijia Jiang, W Guo, Bastien Douhard, Alain Moussa, H Bender, Wilfried Vandervorst, M HeynsAbstract:We report two approaches to integrate high quality III-V templates by epitaxial growth with low defectivity on Si wafers. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagation from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.
Sijia Jiang - One of the best experts on this subject based on the ideXlab platform.
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heteroepitaxy of inp on si 001 by selective area metal organic vapor phase epitaxy in sub 50 nm width Trenches the role of the nucleation layer and the recess engineering
Journal of Applied Physics, 2014Co-Authors: Clement Merckling, Aaron Thean, Nadine Collaert, Niamh Waldron, Sijia Jiang, W Guo, Matty Caymax, E Vancoille, K Barla, Marc HeynsAbstract:This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in Shallow Trench Isolation Trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.
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selective area growth of inp in Shallow Trench Isolation on large scale si 001 wafer using defect confinement technique
Journal of Applied Physics, 2013Co-Authors: Clement Merckling, Niamh Waldron, Sijia Jiang, W Guo, O Richard, Bastien Douhard, Alain Moussa, D Vanhaeren, H Bender, Nadine CollaertAbstract:Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the Trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the Trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III–V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III–V virtual substrates on large-scale Si substrates.
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towards the monolithic integration of iii v compound semiconductors on si selective area growth in high aspect ratio structures vs strain relaxed buffer mediated epitaxy
Compound Semiconductor Integrated Circuit Symposium, 2012Co-Authors: M Cantoro, Clement Merckling, Niamh Waldron, Sijia Jiang, W Guo, Bastien Douhard, Alain Moussa, H Bender, Wilfried Vandervorst, M HeynsAbstract:We report two approaches to integrate high quality III-V templates by epitaxial growth with low defectivity on Si wafers. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagation from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.
Niamh Waldron - One of the best experts on this subject based on the ideXlab platform.
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heteroepitaxy of inp on si 001 by selective area metal organic vapor phase epitaxy in sub 50 nm width Trenches the role of the nucleation layer and the recess engineering
Journal of Applied Physics, 2014Co-Authors: Clement Merckling, Aaron Thean, Nadine Collaert, Niamh Waldron, Sijia Jiang, W Guo, Matty Caymax, E Vancoille, K Barla, Marc HeynsAbstract:This study relates to the heteroepitaxy of InP on patterned Si substrates using the defect trapping technique. We carefully investigated the growth mechanism in Shallow Trench Isolation Trenches to optimize the nucleation layer. By comparing different recess engineering options: rounded-Ge versus V-grooved, we could show a strong enhancement of the crystalline quality and growth uniformity of the InP semiconductor. The demonstration of III-V heteroepitaxy at scaled dimensions opens the possibility for new applications integrated on Silicon.
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selective area growth of inp in Shallow Trench Isolation on large scale si 001 wafer using defect confinement technique
Journal of Applied Physics, 2013Co-Authors: Clement Merckling, Niamh Waldron, Sijia Jiang, W Guo, O Richard, Bastien Douhard, Alain Moussa, D Vanhaeren, H Bender, Nadine CollaertAbstract:Heterogeneous integration of III–V semiconductors on Si substrate has been attracting much attention as building blocks for next-generation electronics, optoelectronics, and photonics. In the present paper, we studied the selective area epitaxial studies of InP grown on 300 mm on-axis Si (001) substrates patterned with Shallow Trench Isolation (STI) using the necking effect technique to trap crystalline defects on the sidewalls. We make use of a thin Ge buffer in the bottom of the Trench to reduce interfacial strain at the interface and to promote InP nucleation. We could show here, by systematic analysis, the strong impact of the growth temperatures and pressures of the InP layer on the growth uniformity along the Trench and crystalline quality that we correlated with resistance changes and interdiffusion measured in the III–V layer. The key challenge remains in the ultimate control of crystalline quality during InP selective growth in order to reduce defect density to enable device-quality III–V virtual substrates on large-scale Si substrates.
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towards the monolithic integration of iii v compound semiconductors on si selective area growth in high aspect ratio structures vs strain relaxed buffer mediated epitaxy
Compound Semiconductor Integrated Circuit Symposium, 2012Co-Authors: M Cantoro, Clement Merckling, Niamh Waldron, Sijia Jiang, W Guo, Bastien Douhard, Alain Moussa, H Bender, Wilfried Vandervorst, M HeynsAbstract:We report two approaches to integrate high quality III-V templates by epitaxial growth with low defectivity on Si wafers. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagation from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.
