The Experts below are selected from a list of 315 Experts worldwide ranked by ideXlab platform
Mona M. Hella - One of the best experts on this subject based on the ideXlab platform.
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A 30–75 $\text{dB}\Omega$ 2.5 GHz 0.13-$\mu\text{m}$ CMOS Receiver Front-End With Large Input Capacitance Tolerance for Short-Range Optical Communication
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016Co-Authors: Sagar Ray, Mona M. HellaAbstract:This paper describes the design and implementation of a linear optical receiver front-end for short range optical communication applications in 0.13-μm CMOS technology. While conventional optical receivers are typically implemented using limiting amplifiers (LA), emerging optical systems are expected to employ advanced modulation schemes, which require preserving the signal envelope. The proposed linear optical receiver architecture utilizes super-Gm transimpedance amplification with common-mode restoration and constant settling time automatic gain control (AGC) with background illumination cancellation to preserve the signal linearity while tolerating Capacitance up to 15 pF for large area photo-detectors. Linearity aware design of transimpedance amplifiers (TIA), variable gain control (VGA), and post amplifiers (PA) are discussed before introducing an exponential generator based on the parasitic BJTs available in the used technology. Consuming 40 mW from a 1.2 V supply in the presence of ~15 pF Input Capacitance, the circuit achieves a binary modulation data rate of 5 Gbps with an Input sensitivity of ~ 65 μA maintaining a bit-error rate (BER) <; 10-12. S-parameter measurements show a constant -3 dB bandwidth of 2.5 GHz for a wide dynamic range of ~45 dB (30-75 dBΩ) with dB-linearity error better than ±1 dB. To demonstrate the optical functionality of the architecture, an external photodiode (PDCS70T-GS) is directly wirebonded to the chip. Optical measurements confirm a sensitivity of -9.5 dBm (BER <; 10-12) at a highest data rate of 5 Gb/s (λ = 680 nm). The noise and linearity performance of the receiver is verified using Input referred integrated noise and 1 dB-compression point measurements for different gain settings.
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A 30–75 $\text{dB}\Omega$ 2.5 GHz 0.13-$\mu\text{m}$ CMOS Receiver Front-End With Large Input Capacitance Tolerance for Short-Range Optical Communication
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016Co-Authors: Mona M. HellaAbstract:This paper describes the design and implementation of a linear optical receiver front-end for short range optical communication applications in 0.13-μm CMOS technology. While conventional optical receivers are typically implemented using limiting amplifiers (LA), emerging optical systems are expected to employ advanced modulation schemes, which require preserving the signal envelope. The proposed linear optical receiver architecture utilizes super-Gm transimpedance amplification with common-mode restoration and constant settling time automatic gain control (AGC) with background illumination cancellation to preserve the signal linearity while tolerating Capacitance up to 15 pF for large area photo-detectors. Linearity aware design of transimpedance amplifiers (TIA), variable gain control (VGA), and post amplifiers (PA) are discussed before introducing an exponential generator based on the parasitic BJTs available in the used technology. Consuming 40 mW from a 1.2 V supply in the presence of ~15 pF Input Capacitance, the circuit achieves a binary modulation data rate of 5 Gbps with an Input sensitivity of ~ 65 μA maintaining a bit-error rate (BER)
Sagar Ray - One of the best experts on this subject based on the ideXlab platform.
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A 30–75 $\text{dB}\Omega$ 2.5 GHz 0.13-$\mu\text{m}$ CMOS Receiver Front-End With Large Input Capacitance Tolerance for Short-Range Optical Communication
IEEE Transactions on Circuits and Systems I: Regular Papers, 2016Co-Authors: Sagar Ray, Mona M. HellaAbstract:This paper describes the design and implementation of a linear optical receiver front-end for short range optical communication applications in 0.13-μm CMOS technology. While conventional optical receivers are typically implemented using limiting amplifiers (LA), emerging optical systems are expected to employ advanced modulation schemes, which require preserving the signal envelope. The proposed linear optical receiver architecture utilizes super-Gm transimpedance amplification with common-mode restoration and constant settling time automatic gain control (AGC) with background illumination cancellation to preserve the signal linearity while tolerating Capacitance up to 15 pF for large area photo-detectors. Linearity aware design of transimpedance amplifiers (TIA), variable gain control (VGA), and post amplifiers (PA) are discussed before introducing an exponential generator based on the parasitic BJTs available in the used technology. Consuming 40 mW from a 1.2 V supply in the presence of ~15 pF Input Capacitance, the circuit achieves a binary modulation data rate of 5 Gbps with an Input sensitivity of ~ 65 μA maintaining a bit-error rate (BER) <; 10-12. S-parameter measurements show a constant -3 dB bandwidth of 2.5 GHz for a wide dynamic range of ~45 dB (30-75 dBΩ) with dB-linearity error better than ±1 dB. To demonstrate the optical functionality of the architecture, an external photodiode (PDCS70T-GS) is directly wirebonded to the chip. Optical measurements confirm a sensitivity of -9.5 dBm (BER <; 10-12) at a highest data rate of 5 Gb/s (λ = 680 nm). The noise and linearity performance of the receiver is verified using Input referred integrated noise and 1 dB-compression point measurements for different gain settings.
Gert Cauwenberghs - One of the best experts on this subject based on the ideXlab platform.
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A 6.5- $\mu \text{W}$ /MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2016Co-Authors: Siddharth Joshi, Gert CauwenberghsAbstract:This brief presents a CMOS charge buffer with femtofarad-range Input Capacitance for applications in capacitive electropotential sensing. We analyze and verify a feedback mechanism to negate parasitic Capacitances seen at the Input of a CMOS amplifier. Measurements are presented from a prototype fabricated in 65-nm CMOS occupying an active area of 193 $ {\mu }\text{m}^{{2}}$ with an efficiency of 6.5 $ {\mu }\text{W}$ /MHz. Over-the-air measurements validate its applicability to electropotential sensing.
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a 6 5 mu text w mhz charge buffer with 7 ff Input Capacitance in 65 nm cmos for noncontact electropotential sensing
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2016Co-Authors: Siddharth Joshi, Gert CauwenberghsAbstract:This brief presents a CMOS charge buffer with femtofarad-range Input Capacitance for applications in capacitive electropotential sensing. We analyze and verify a feedback mechanism to negate parasitic Capacitances seen at the Input of a CMOS amplifier. Measurements are presented from a prototype fabricated in 65-nm CMOS occupying an active area of 193 $ {\mu }\text{m}^{{2}}$ with an efficiency of 6.5 $ {\mu }\text{W}$ /MHz. Over-the-air measurements validate its applicability to electropotential sensing.
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A 6.5- $\mu \text{W}$ /MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016Co-Authors: Siddharth Joshi, Gert CauwenberghsAbstract:This brief presents a CMOS charge buffer with femtofarad-range Input Capacitance for applications in capacitive electropotential sensing. We analyze and verify a feedback mechanism to negate parasitic Capacitances seen at the Input of a CMOS amplifier. Measurements are presented from a prototype fabricated in 65-nm CMOS occupying an active area of 193 μm2 with an efficiency of 6.5 μW/MHz. Over-the-air measurements validate its applicability to electropotential sensing.
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Micropower non-contact EEG electrode with active common-mode noise suppression and Input Capacitance cancellation
2009 Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2009Co-Authors: Gert CauwenberghsAbstract:A non-contact EEG electrode with Input Capacitance neutralization and common-mode noise suppression circuits is presented. The coin sized sensor capacitively couples to the scalp without direct contact to the skin. To minimize the effect of signal attenuation and channel gain mismatch, the Input Capacitance of each sensor is actively neutralized using positive feedback and bootstrapping. Common-mode suppression is achieved through a single conductive sheet to establish a common mode reference. Each sensor electrode provides a differential gain of 60 dB. Signals are transmitted in a digital serial daisy-chain directly from a local 16-bit ADC, minimizing the number of wires required to establish a high density EEG sensor network. The micropower electrode consumes only 600 muW from a single 3.3 V supply.
G Pessina - One of the best experts on this subject based on the ideXlab platform.
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a very simple method to measure the Input Capacitance and the Input current of transistors
Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment, 2001Co-Authors: A Fascilla, G PessinaAbstract:Abstract We describe a method to measure the gate Capacitance and the gate current of transistors at any temperature and at any operating condition. Discrimination between the total Input Capacitance and transfer reverse Capacitance (gate to drain Capacitance) is also possible with high accuracy. With this data the optimization of the signal to noise ratio and power dissipation can be achieved in the design of the front-end electronics for nuclear applications.
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Monolithic read-out electronics for the silicon calorimeters at SSC/LHC colliders
Nuclear Physics B - Proceedings Supplements, 1991Co-Authors: A. Gola, G Pessina, Pg Rancoita, G. TerziAbstract:Abstract A very fast monolithic charge sensitive preamplifier using HF2CMOS technology featuring less than 45mW power dissipation for a 5V maximum output voltage swing, with a slew rate about 700V/μsec for 150pF Input Capacitance (≈ 7nsec rise time), has been realized. A front-end set up for the read out of more detectors and the shaping of the signal with a 20nsec RC-CR filter employing only monolithic preamplifiers is described and tested. The measured value of ENC (Electronic Noise Charge) for the arrangement with 150pF Input Capacitance is 17keRMS. The preamplifier meets the requirements for silicon calorimetry application for experiments at the hadron colliders SSC/LHC.
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FAST FRONT-END ELECTRONICS FOR EXPERIMENTS USING SILICON CALORIMETERS AT SSC /LHC COLLIDERS
Nuclear Instruments & Methods in Physics Research Section A-accelerators Spectrometers Detectors and Associated Equipment, 1990Co-Authors: A. Gola, G Pessina, Pg RancoitaAbstract:Abstract A fast VLSI preamplifier using HF2CMOS technology was designed and built. The preamplifier meets the requirements for silicon calorimetry application in experiments at hadron colliders SSC/LHC. The overall power consumption is less than 45 mW for a maximum output voltage swing of 5 V (≈ 7 ns rise time). The slew rate is about 700 V/μs for an Input Capacitance of 150 pF. The measured value of ENC (equivalent noise charge), for an RC-CR shaping time of 20 ns and an Input Capacitance of 150 pF, is 17 ke RMS .
Martin Margala - One of the best experts on this subject based on the ideXlab platform.
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A Self-Biased Charge-Transfer Sense Amplifier
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Sandeep Patil, Michael Wieckowski, Martin MargalaAbstract:A self-biased charge-transfer sense amplifier (SB-CTSA) is proposed for applications in high performance static memory. The new design incorporates an internal biasing mechanism along with a static output latch that can store the result from a read cycle indefinitely at no additional cost in power. It exhibits 23% faster sensing delay and a 37% reduction in read energy when compared to a recently proposed CTSA structure. In addition, the SB-CTSA design exhibits low sensitivity to both Input Capacitance and Input Capacitance mismatch.
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ISCAS - A Self-Biased Charge-Transfer Sense Amplifier
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Sandeep Patil, Michael Wieckowski, Martin MargalaAbstract:A self-biased charge-transfer sense amplifier (SB-CTSA) is proposed for applications in high performance static memory. The new design incorporates an internal biasing mechanism along with a static output latch that can store the result from a read cycle indefinitely at no additional cost in power. It exhibits 23% faster sensing delay and a 37% reduction in read energy when compared to a recently proposed CTSA structure. In addition, the SB-CTSA design exhibits low sensitivity to both Input Capacitance and Input Capacitance mismatch.