The Experts below are selected from a list of 285 Experts worldwide ranked by ideXlab platform
Jih-ching Chiu - One of the best experts on this subject based on the ideXlab platform.
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A relation-exchanging buffering mechanism for Instruction and data Streaming
Computers & Electrical Engineering, 2013Co-Authors: Jih-ching Chiu, Kaiming Yang, Yu-liang Chou, Chih-kang WuAbstract:Abstract The traditional memory hierarchy design can smooth the data Stream and Instruction Stream. However, the bandwidth of the Instruction Stream and data Stream are still the main challenge for high-performance microprocessor systems. To improve the data and Instruction fetchers, the proposed buffering architecture can exploits both the temporal and spatial localities with a relation-exchanging buffering mechanism. On buffers hit, the dynamic sequences of Instruction or data can be reused. At the same time, the prefetching mechanism will be enabled to prefetch the Instruction/data being used in the near future. According to the simulation results, the proposed buffering mechanism with the depth 3 and 64-byte line size, which only needs extra 4% hardware cost, is a cost-ineffectiveness choice. The hit rate of an ABP buffer can 22% outperforms that of loop buffer architecture to fetch Instruction Stream and 7% outperform that of FIFO strategy to fetch data Stream.
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The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA
Journal of Information Science and Engineering, 2010Co-Authors: Jih-ching Chiu, Yu-liang ChouAbstract:The potential performance of superscalar processors can be exploited only when processor is fed with sufficient Instruction bandwidth. The front-end units, the Instruction Stream Buffer (ISB) and the fetcher, are the key elements for achieving this goal. Current ISBs could not support Instruction Streaming beyond a basic block. In x86 processors, the split-line Instruction problem worsens this situation. In this paper, we proposed a basic blocks reassembling ISB. By cooperating with the proposed Line-Weighted Branch Target Buffer (LWBTB), the proposed ISB can predict upcoming branch information and reassemble current cache line together with the other cache line containing Instructions for the next basic block. Therefore, the fetcher could fetch more Instructions in a cycle with the assistance of the proposed ISB. Simulation results show that the cache line size over 64 bytes has a good chance to let two basic blocks present in a reassembled cache line and the fetch efficiency is about 90% as the fetch capacity is under 6.
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a novel Instruction Stream buffer for vliw architectures
Computers & Electrical Engineering, 2010Co-Authors: Jih-ching Chiu, Kaiming YangAbstract:The Instruction compression mechanism used to solve the drawbacks of traditional very long Instruction word (VLIW) architectures often leads to poor code density in the Instruction cache, which causes the irregular lengths of long Instructions to cross the different cache line. These split long Instructions cannot be fetched simultaneously, which creates a bottleneck for VLIW architectures. This paper proposes a buffing mechanism which can slide the split long Instruction as a continuous form to offer better efficiency in Instruction fetching. This approach helps maintain the behaviors of the software pipeline technology, which schedules iterative Instructions to enhance the performance of Streaming processing for VLIW architectures. In the proposed mechanism, the Instruction Stream buffer stores the repeat block completely and suspends as far as possible the cache access to reduce access time. The advantages of repeatedly issuing Instructions in the Instruction buffer and preventing split long Instructions, can substantially improve the performance in fetching Instructions. Simulation results show that the mechanism is efficient at the Instruction level for the basic DSP/IMG library by improving performance by 35% on average.
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ACSAC - Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA
2008 13th Asia-Pacific Computer Systems Architecture Conference, 2008Co-Authors: Jih-ching Chiu, Yu-liang ChouAbstract:The potential performance of superscalar processors can be exploited only when processor is fed with sufficient Instruction bandwidth. The front-end units, the Instruction Stream Buffer (ISB) and the fetcher, are the key elements for achieving this goal. Current ISBs cannot support Instruction Streaming beyond a basic block. In X86 processors, the split-line Instruction problem worsens this situation. We proposed a basic blocks reassembling ISB in this paper. By cooperating with the proposed Line Weighted Branch Target Buffer (LWBTB), the ISB can predict advance branch information and reassemble cache lines. Front-End could fetch more valid Instructions in a cycle by reassembling the original line containing Instructions for the next basic block. Simulation results show that the cache line size over 64 bytes has a good chance to let two basic blocks in the reassembled Instruction line and the fetch efficiency is about 90% as the fetch capacity is under 6.
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Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA
2008 13th Asia-Pacific Computer Systems Architecture Conference, 2008Co-Authors: Jih-ching Chiu, Yu-liang ChouAbstract:The potential performance of superscalar processors can be exploited only when processor is fed with sufficient Instruction bandwidth. The front-end units, the Instruction Stream Buffer (ISB) and the fetcher, are the key elements for achieving this goal. Current ISBs cannot support Instruction Streaming beyond a basic block. In X86 processors, the split-line Instruction problem worsens this situation. We proposed a basic blocks reassembling ISB in this paper. By cooperating with the proposed Line Weighted Branch Target Buffer (LWBTB), the ISB can predict advance branch information and reassemble cache lines. Front-End could fetch more valid Instructions in a cycle by reassembling the original line containing Instructions for the next basic block. Simulation results show that the cache line size over 64 bytes has a good chance to let two basic blocks in the reassembled Instruction line and the fetch efficiency is about 90% as the fetch capacity is under 6.
J.j. Serrano - One of the best experts on this subject based on the ideXlab platform.
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A watchdog processor architecture with minimal performance overhead
Lecture Notes in Computer Science, 2020Co-Authors: Francisco J. Rodriguez, J.c. Campelo, J.j. SerranoAbstract:Control flow monitoring using a watchdog processor is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor Instruction Stream creating noticeable memory and performance overheads. A novel watchdog processor architecture using embedded signatures is presented that minimizes the memory over-head and nullifies performance penalty on the main processor without sacrificing error detection coverage or latency. This scheme is called Interleaved Signature Instruction Stream (ISIS) in order to reflect the fact that signatures and main Instructions are two independent Streams that co-exist in the system.
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Improving the interleaved signature Instruction Stream technique
CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436), 2003Co-Authors: F. Rodriguez, J.c. Campelo, J.j. SerranoAbstract:Control flow monitoring using a watchdog processor is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor Instruction Stream creating noticeable memory and performance overheads. A novel embedding signatures technique called interleaved signatures Instruction Stream has been recently presented. Targeted to processors included into field-programmable devices, its main goal is to reduce the performance penalty produced by the watchdog processor in previous proposals. The work presented here is an improvement of this technique and offers a solution to the memory overhead without sacrificing performance, thus yielding a better overall architecture. We have called this improved technique OSIRIS: another interleaved signature Instruction Stream.
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DFT - A memory overhead evaluation of the interleaved signature Instruction Stream
17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2002. DFT 2002. Proceedings., 2002Co-Authors: F. Rodriguez, J.c. Campelo, J.j. SerranoAbstract:Using a watchdog processor for concurrent error detection of a processor execution flow is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor Instruction Stream creating noticeable memory and performance overheads. The interleaved signature Instruction Stream (ISIS) technique is a signature embedding technique that allows signatures to co-exist with the main Instruction Stream with a minimal impact on processor performance, without sacrificing error detection coverage or latency. This technique has been implemented into HORUS, a MIPS-like RISC processor developed in VHDL. This paper presents the HORUS architecture novelties demanded by ISIS, discusses the performance impact of adding an ISIS watchdog processor and provides results of ISIS memory overhead. These results are compared against similar solutions previously presented in the literature.
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SAFECOMP - A Watchdog Processor Architecture with Minimal Performance Overhead
Computer Safety Reliability and Security, 2002Co-Authors: Francisco J. Rodriguez, J.c. Campelo, J.j. SerranoAbstract:Control flow monitoring using a watchdog processor is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor Instruction Stream creating noticeable memory and performance overheads. A novel watchdog processor architecture using embedded signatures is presented that minimizes the memory overhead and nullifies performance penalty on the main processor without sacrificing error detection coverage or latency. This scheme is called Interleaved Signature Instruction Stream (ISIS) in order to reflect the fact that signatures and main Instructions are two independent Streams that co-exist in the system.
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A memory overhead evaluation of the interleaved signature Instruction Stream
17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems 2002. DFT 2002. Proceedings., 2002Co-Authors: F. Rodriguez, J.c. Campelo, J.j. SerranoAbstract:Using a watchdog processor for concurrent error detection of a processor execution flow is a well-known technique to increase the dependability of a microprocessor system. Most approaches embed reference signatures for the watchdog processor into the processor Instruction Stream creating noticeable memory and performance overheads. The interleaved signature Instruction Stream (ISIS) technique is a signature embedding technique that allows signatures to co-exist with the main Instruction Stream with a minimal impact on processor performance, without sacrificing error detection coverage or latency. This technique has been implemented into HORUS, a MIPS-like RISC processor developed in VHDL. This paper presents the HORUS architecture novelties demanded by ISIS, discusses the performance impact of adding an ISIS watchdog processor and provides results of ISIS memory overhead. These results are compared against similar solutions previously presented in the literature.
Michael C Shebanow - One of the best experts on this subject based on the ideXlab platform.
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single Instruction Stream parallelism is greater than two
International Symposium on Computer Architecture, 1991Co-Authors: Michael Butler, Yale N Patt, Mitch Kirkpatrick Alsup, Hunter L Scales, Michael C ShebanowAbstract:Recent studies have concluded that little parallelism (less than two operations per cycle) is available in single Instruction Streams. Since the amount of available parallelism should influence the design of the processor, it is important to verify how much parallelism really exists. In this study we model the execution of the SPEC benchmarks under differing resource constraints. We repeat the work of the previous researchers, and show that under the hardware resource constraints they imposed, we get similar results. On the other hand, when all constraints are removed except those ~equired by the semantics oft he program, we have found degrees of parallelism in excess of 17 Instructions per cycle. Finally, and perhaps most important for exploiting single Instruction Stream parallelism now, we show that if the hardware is properly balanced, one can sustain from 2.0 to 5.8 Instructions per cycle on a processor that is reasonable to design today.
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ISCA - Single Instruction Stream parallelism is greater than two
Proceedings of the 18th annual international symposium on Computer architecture - ISCA '91, 1991Co-Authors: Michael Butler, Yale N Patt, Mitch Kirkpatrick Alsup, Hunter L Scales, Michael C ShebanowAbstract:Recent studies have concluded that little parallelism (less than two operations per cycle) is available in single Instruction Streams. Since the amount of available parallelism should influence the design of the processor, it is important to verify how much parallelism really exists. In this study we model the execution of the SPEC benchmarks under differing resource constraints. We repeat the work of the previous researchers, and show that under the hardware resource constraints they imposed, we get similar results. On the other hand, when all constraints are removed except those ~equired by the semantics oft he program, we have found degrees of parallelism in excess of 17 Instructions per cycle. Finally, and perhaps most important for exploiting single Instruction Stream parallelism now, we show that if the hardware is properly balanced, one can sustain from 2.0 to 5.8 Instructions per cycle on a processor that is reasonable to design today.
Chung-ping Chung - One of the best experts on this subject based on the ideXlab platform.
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ICCD - Design of Instruction Stream buffer with trace support for X86 processors
Proceedings 2000 International Conference on Computer Design, 2000Co-Authors: Jih-ching Chiu, I-huan Huang, Chung-ping ChungAbstract:The potential performance of superscalar microprocessors can be exploited only when fed with sufficient Instruction bandwidth. The front-end units, the Instruction Stream buffer and the fetcher, are the key elements achieving this goal. In most current processors, Instruction Stream buffers cannot support the Instruction sequence beyond a basic block. The fetch rates are constrained by the branch barriers. In x86 processors, the split-line Instruction problem worsens this constrain. We propose a design to improve Instruction Stream buffer performance by coupling it with BTB to support trace prediction. According to the simulation results of such an Instruction Stream buffer, the maximum fetch bandwidth can reach 8.42 x86 Instructions per cycle. Furthermore, we suggest that the Instruction Stream buffer consists of two 64-bytes entries. Compared with other existing designs, this Instruction Stream buffer can improve performance by 90% over current x86 processor Instruction fetching on average.
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Design of Instruction Stream buffer with trace support for X86 processors
Proceedings 2000 International Conference on Computer Design, 2000Co-Authors: Jih-ching Chiu, I-huan Huang, Chung-ping ChungAbstract:The potential performance of superscalar microprocessors can be exploited only when fed with sufficient Instruction bandwidth. The front-end units, the Instruction Stream buffer and the fetcher, are the key elements achieving this goal. In most current processors, Instruction Stream buffers cannot support the Instruction sequence beyond a basic block. The fetch rates are constrained by the branch barriers. In x86 processors, the split-line Instruction problem worsens this constrain. We propose a design to improve Instruction Stream buffer performance by coupling it with BTB to support trace prediction. According to the simulation results of such an Instruction Stream buffer, the maximum fetch bandwidth can reach 8.42 x86 Instructions per cycle. Furthermore, we suggest that the Instruction Stream buffer consists of two 64-bytes entries. Compared with other existing designs, this Instruction Stream buffer can improve performance by 90% over current x86 processor Instruction fetching on average.
Gurindar S Sohi - One of the best experts on this subject based on the ideXlab platform.
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Understanding the backward slices of performance degrading Instructions
Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201), 2000Co-Authors: Craig Zilles, Gurindar S SohiAbstract:For many applications, branch mispredictions and cache misses limit a processor's performance to a level well below its peak Instruction throughput. A small fraction of static Instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic Instruction Stream leading up to these performance degrading Instructions to identify the operations necessary to execute them early. The backward slice (the subset of the program that relates to the Instruction) of these performance degrading Instructions, if small compared to the whole dynamic Instruction Stream, can be pre-executed to hide the Instruction's latency. To overcome conservative dependence assumptions that result in large slices, speculation can be used, resulting in speculative slices. This paper provides an initial characterization of the backward slices of L2 data cache misses and branch mispredictions, and shows the effectiveness of techniques, including memory dependence prediction and control independence, for reducing the size of these slices. Through the use of these techniques, many slices can be reduced to less than one tenth of the full dynamic Instruction Stream when considering the 512 Instructions before the performance degrading Instruction.
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ISCA - Understanding the backward slices of performance degrading Instructions
Proceedings of the 27th annual international symposium on Computer architecture - ISCA '00, 2000Co-Authors: Craig Zilles, Gurindar S SohiAbstract:For many applications, branch mispredictions and cache misses limit a processor's performance to a level well below its peak Instruction throughput. A small fraction of static Instructions, whose behavior cannot be anticipated using current branch predictors and caches, contribute a large fraction of such performance degrading events. This paper analyzes the dynamic Instruction Stream leading up to these performance degrading Instructions to identify the operations necessary to execute them early. The backward slice (the subset of the program that relates to the Instruction) of these performance degrading Instructions, if small compared to the whole dynamic Instruction Stream, can be pre-executed to hide the Instruction's latency. To overcome conservative dependance assumptions that result in large slices, speculation can be used, resulting in speculative slices. This paper provides an initial characterization of the backward slices of L2 data cache misses and branch mispredictions, and shows the effectiveness of techniques, including memory dependence prediction and control independence, for reducing the size of these slices. Through the use of these techniques, many slices can be reduced to less than one tenth of the full dynamic Instruction Stream when considering the 512 Instructions before the performance degrading Instruction.