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Kofi A A Makinwa - One of the best experts on this subject based on the ideXlab platform.
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a capacitively coupled chopper Instrumentation Amplifier with a 30v common mode range 160db cmrr and 5μv offset
International Solid-State Circuits Conference, 2012Co-Authors: Qinwen Fan, J H Huijsing, Kofi A A MakinwaAbstract:This paper describes a capacitively coupled chopper Instrumentation Amplifier (CCIA) for current-sensing applications. A capacitively driven input chopper enables a ±30V input common-mode (CM) range and an input offset less than 5μV. The CCIA does not draw supply current from its input terminals or require a separate high-voltage (HV) supply; and has a common-mode rejection ratio (CMRR) in excess of 160dB, both of which represent significant improvements on the state-of-the-art [1–3]. Implemented in a HV CMOS 0.7μm technology, the CCIA achieves an NEF of 6.1 (6.5× better than [1–3]), while drawing only 26μA from a 3V supply.
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a 21 nv surd hz chopper stabilized multi path current feedback Instrumentation Amplifier with 2 mu v offset
IEEE Journal of Solid-state Circuits, 2012Co-Authors: J H Huijsing, Kofi A A MakinwaAbstract:This paper describes the design of a precision Instrumentation Amplifier. It employs chopping to reduce its offset and 1/f noise, and the resulting ripple caused by the up-modulated offset and 1/f noise is suppressed by a ripple reduction loop. A multi-path architecture is used to eliminate the transfer function notch that would otherwise be introduced by the ripple reduction loop. The Amplifier is implemented in a standard 0.7 μm CMOS technology and draws 143 μA current from a 5 V supply. Its input-referred noise is 21 nV/√Hz and its residual offset is less than 2× μV (12 samples). The Instrumentation Amplifier can also be configured as a general-purpose opamp with half the noise and offset, but which dissipates the same amount of power.
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input characteristics of a chopped multi path current feedback Instrumentation Amplifier
IEEE International Workshop on Advances in Sensors and Interfaces, 2011Co-Authors: J H Huijsing, Kofi A A MakinwaAbstract:This paper presents simulations and measurements of the input impedance, input bias and offset current of a chopped multi-path current feedback Instrumentation Amplifier. In precision applications, these parameters, together with a finite impedance source can lead to significant measurement errors. In this paper, design strategies to minimize these errors are provided. At a chopping frequency of 30 kHz, the proposed Amplifier has an input impedance of 6 MΩ, with bias and offset currents of 102pA and 43pA, respectively. In addition, it achieves low noise (21nV/√Hz), low (2 µV) input-referred offset, high common-mode rejection ratio (134dB) and high power supply rejection ratio (120dB).
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a ping pong pang current feedback Instrumentation Amplifier with 0 04 gain error
Symposium on VLSI Circuits, 2011Co-Authors: Saket Sakunia, Frerik Witte, Michiel A P Pertijs, Kofi A A MakinwaAbstract:A ping-pong-pang auto-zeroed and chopped current-feedback Instrumentation Amplifier (CFIA) uses three dynamically-matched input stages to achieve 0.04% gain error, a 2.5× improvement over prior art. Its 4µV offset and 28nV/√Hz noise are achieved at 3.5× less supply current than a comparable ping-pong auto-zeroed CFIA.
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a 1 8 mu w 60 nv surd hz capacitively coupled chopper Instrumentation Amplifier in 65 nm cmos for wireless sensor nodes
IEEE Journal of Solid-state Circuits, 2011Co-Authors: Qinwen Fan, J H Huijsing, Fabio Sebastiano, Kofi A A MakinwaAbstract:This paper presents a low-power precision Instrumentation Amplifier intended for use in wireless sensor nodes. It employs a capacitively-coupled chopper topology to achieve a rail-to-rail input common-mode range as well as high power efficiency. A positive feedback loop is employed to boost its input impedance, while a ripple reduction loop suppresses the chopping ripple. To facilitate bio-potential sensing, an optional DC servo loop may be employed to suppress electrode offset. The IA achieves 1 μV offset, 0.16% gain inaccuracy, 134 dB CMRR, 120 dB PSRR and a noise efficiency factor of 3.3. The Instrumentation Amplifier was implemented in a 65 nm CMOS technology. It occupies only 0.1 mm2 chip area (0.2 mm2 with the DC servo loop) and consumes 1.8 μA current (2.1 μA with the DC servo loop) from a 1 V supply.
J H Huijsing - One of the best experts on this subject based on the ideXlab platform.
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a capacitively coupled chopper Instrumentation Amplifier with a 30v common mode range 160db cmrr and 5μv offset
International Solid-State Circuits Conference, 2012Co-Authors: Qinwen Fan, J H Huijsing, Kofi A A MakinwaAbstract:This paper describes a capacitively coupled chopper Instrumentation Amplifier (CCIA) for current-sensing applications. A capacitively driven input chopper enables a ±30V input common-mode (CM) range and an input offset less than 5μV. The CCIA does not draw supply current from its input terminals or require a separate high-voltage (HV) supply; and has a common-mode rejection ratio (CMRR) in excess of 160dB, both of which represent significant improvements on the state-of-the-art [1–3]. Implemented in a HV CMOS 0.7μm technology, the CCIA achieves an NEF of 6.1 (6.5× better than [1–3]), while drawing only 26μA from a 3V supply.
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a 21 nv surd hz chopper stabilized multi path current feedback Instrumentation Amplifier with 2 mu v offset
IEEE Journal of Solid-state Circuits, 2012Co-Authors: J H Huijsing, Kofi A A MakinwaAbstract:This paper describes the design of a precision Instrumentation Amplifier. It employs chopping to reduce its offset and 1/f noise, and the resulting ripple caused by the up-modulated offset and 1/f noise is suppressed by a ripple reduction loop. A multi-path architecture is used to eliminate the transfer function notch that would otherwise be introduced by the ripple reduction loop. The Amplifier is implemented in a standard 0.7 μm CMOS technology and draws 143 μA current from a 5 V supply. Its input-referred noise is 21 nV/√Hz and its residual offset is less than 2× μV (12 samples). The Instrumentation Amplifier can also be configured as a general-purpose opamp with half the noise and offset, but which dissipates the same amount of power.
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input characteristics of a chopped multi path current feedback Instrumentation Amplifier
IEEE International Workshop on Advances in Sensors and Interfaces, 2011Co-Authors: J H Huijsing, Kofi A A MakinwaAbstract:This paper presents simulations and measurements of the input impedance, input bias and offset current of a chopped multi-path current feedback Instrumentation Amplifier. In precision applications, these parameters, together with a finite impedance source can lead to significant measurement errors. In this paper, design strategies to minimize these errors are provided. At a chopping frequency of 30 kHz, the proposed Amplifier has an input impedance of 6 MΩ, with bias and offset currents of 102pA and 43pA, respectively. In addition, it achieves low noise (21nV/√Hz), low (2 µV) input-referred offset, high common-mode rejection ratio (134dB) and high power supply rejection ratio (120dB).
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a 1 8 mu w 60 nv surd hz capacitively coupled chopper Instrumentation Amplifier in 65 nm cmos for wireless sensor nodes
IEEE Journal of Solid-state Circuits, 2011Co-Authors: Qinwen Fan, J H Huijsing, Fabio Sebastiano, Kofi A A MakinwaAbstract:This paper presents a low-power precision Instrumentation Amplifier intended for use in wireless sensor nodes. It employs a capacitively-coupled chopper topology to achieve a rail-to-rail input common-mode range as well as high power efficiency. A positive feedback loop is employed to boost its input impedance, while a ripple reduction loop suppresses the chopping ripple. To facilitate bio-potential sensing, an optional DC servo loop may be employed to suppress electrode offset. The IA achieves 1 μV offset, 0.16% gain inaccuracy, 134 dB CMRR, 120 dB PSRR and a noise efficiency factor of 3.3. The Instrumentation Amplifier was implemented in a 65 nm CMOS technology. It occupies only 0.1 mm2 chip area (0.2 mm2 with the DC servo loop) and consumes 1.8 μA current (2.1 μA with the DC servo loop) from a 1 V supply.
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a 21nv hz chopper stabilized multipath current feedback Instrumentation Amplifier with 2µv offset
International Solid-State Circuits Conference, 2010Co-Authors: J H Huijsing, Kofi A A MakinwaAbstract:Amplifiers with low offset and low 1/f noise usually employ auto-zeroing (AZ) and/or chopping. However, AZ suffers from noise aliasing, and so requires more power dissipation for a given noise specification. Chopping, although free of noise aliasing, requires notch filters [1, 2] or AZ [3] to remove the ripple caused by up-modulated offset and 1/f noise. This paper describes a chopper-stabilized multi-path current-feedback Instrumentation Amplifier (CFIA), whose ripple is removed by a continuous-time (CT) ripple-reduction loop (RRL) [2]. In contrast to [2], the notch created by the RRL is eliminated by the use of a multi-path architecture. This results in a CFIA with a smooth single-pole response, which also achieves low offset (2µV) and low noise (21nV/√Hz) in a power efficient manner (NEF=9.6). By appropriately connecting its inputs, the CFIA can also be used as an opamp. In this configuration, its offset is further reduced while its noise and NEF are halved.
J F Witte - One of the best experts on this subject based on the ideXlab platform.
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a chopper and auto zero offset stabilized cmos Instrumentation Amplifier
Symposium on VLSI Circuits, 2009Co-Authors: J F Witte, J H Huijsing, Kofi A A MakinwaAbstract:This paper describes a CMOS Instrumentation Amplifier with a noise density of 42nV/νHz and 640kHz GBW at 325µA supply current. It achieves 2.5µV input offset voltage, 130dB CMRR, and 114dB PSRR by the combined use of chopping, auto-zeroing and a current-feedback topology.
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a current feedback Instrumentation Amplifier with 5 mu hbox v offset for bidirectional high side current sensing
IEEE Journal of Solid-state Circuits, 2008Co-Authors: J F Witte, J H Huijsing, Kofi A A MakinwaAbstract:This paper describes an Instrumentation Amplifier for bidirectional high-side current-sensing applications. It uses a multipath indirect current-feedback topology. To achieve low offset, the Amplifier employs a combination of chopping and auto-zeroing in a low frequency path to cancel the offset of a wide-band Amplifier in a high frequency path. With a 60 kHz chopper clock and a 30 kHz auto-zero clock, this offset-stabilization scheme results in an offset voltage of less than 5 muV , a CMRR of 143 dB and a common-mode input voltage range from 1.9 to 30 V. The input voltage-to-current (V-I) converters required by the current-feedback topology are implemented with composite transistors, whose transconductance is determined by laser-trimmed resistors. This results in a less than 0.1% gain inaccuracy. The Instrumentation Amplifier was realized in a 0.8 mum BiCMOS process with high voltage transistors, and has an effective chip area of 2.5 mm2 .
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a current feedback Instrumentation Amplifier with 5μv offset for bidirectional high side current sensing
International Solid-State Circuits Conference, 2008Co-Authors: J F Witte, J H Huijsing, Kofi A A MakinwaAbstract:In this paper, a current-feedback Instrumentation Amplifier for bidirectional high-side current-sensing is proposed. The current sense Amplifier was fabricated in a 0.8mum BICMOS process with high-voltage transistors and laser-trimmed thin-film resistors. It is concluded that these Amplifiers offer a new level of precision in current sensing.
Qiuting Huang - One of the best experts on this subject based on the ideXlab platform.
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a fully integrated untrimmed cmos Instrumentation Amplifier with submicrovolt offset
IEEE Journal of Solid-state Circuits, 1999Co-Authors: Christian Menolfi, Qiuting HuangAbstract:A low-noise CMOS Instrumentation Amplifier intended for low-frequency thermoelectric microsensor applications is presented that achieves submicrovolt offset and noise. Key to its performance is the chopper modulation technique combined with a bandpass filter and a matching on-chip oscillator. No external components or trimming are required. The achievable offset performance depends on the bandpass filter Q and the oscillator-to-bandpass filter matching accuracy. Constraints are derived for an optimum Q and a given matching accuracy. The improvement of common-mode rejection ratio (CMRR) in chopper Amplifiers is discussed. The Amplifier features a total gain of 77/spl plusmn/0.3 dB and a bandwidth of approximately 600 Hz. The measured low-frequency input noise is 8.5 nV//spl radic/Hz and the input offset is 600 nV. The measured low-frequency CMRR is better than 150 dB. The circuit has been implemented in a standard 1-/spl mu/m single-poly CMOS process.
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A low-noise CMOS Instrumentation Amplifier for thermoelectric infrared detectors
IEEE Journal of Solid-State Circuits, 1997Co-Authors: Christian Menolfi, Qiuting HuangAbstract:A low-noise CMOS Instrumentation Amplifier for low-frequency thermoelectric infrared sensor applications is described which uses a chopper technique to reduce low-frequency noise and offset. The offset reduction efficiency of the band-pass filter, implemented to reduce residual offset due to clock feedthrough, has been analyzed and experimentally verified. The circuit has been integrated in a transistor-only 1-μm single-poly n-well CMOS process. It features a gain of 52 dB with a 500 Hz bandwidth and a common-mode rejection ratio (CMRR) of more than 70 dB. The equivalent input low frequency noise is 15 nV/√Hz. The typical residual input offset is 1.5 μV. The Amplifier power consumption is 1.3 mW
Amine Bermak - One of the best experts on this subject based on the ideXlab platform.
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An ultra low-power capacitively-coupled chopper Instrumentation Amplifier for wheatstone-bridge readout circuits
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017Co-Authors: Moaaz Ahmed, Farid Boussaid, Amine BermakAbstract:This paper presents an ultra-low-power low-noise Capacitively-coupled Chopper Instrumentation Amplifier (CCIA). A current-reuse telescopic topology in the first stage along with a recycling folded-cascode topology in the second stage consumes net bias current of 26μA with enhanced efficiency and achieves an input-referred noise power-spectral-density of 12.77nV/√Hz. The proposed CCIA is chopped at 50kHz to bring the input-referred offset around 6μV and flicker-noise corner around 400mHz. Implemented in chartered 0.18μm CMOS process and designed for Thermoresistive Micro Calorimetric Flow (TMCF) sensors, the reported work achieves an excellent Noise Efficiency Factor (NEF) of 2.5 which is the lowest ever reported NEF for such applications.
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a nested chopped current feedback Instrumentation Amplifier for mems flow sensors
International Midwest Symposium on Circuits and Systems, 2016Co-Authors: Moaaz Ahmed, Saqib Mohamad, Amine BermakAbstract:A nested chopped current-feedback Instrumentation Amplifier (CFIA) designed for micro-fluidic applications is reported in this work. The proposed CFIA is chopped at 50kHz to bring input-referred offset below 12μV and flicker-noise corner around 100mHz. In order to further suppress the residue offset to nV-level, the CFIA is again chopped with a slower clock of 500Hz to achieve an input-referred offset of 149nV. The CMOS readout interface for MEMS flow sensor achieves a thermal-noise power spectral density of 4.34nV/√Hz for realizing over 12-bits dynamic range. Implemented in chartered 0.18μm CMOS process, the CFIA draws 522μΑ supply current and achieves an excellent noise efficiency factor (NEF) of 3.82 which is the lowest ever reported with CFIAs.
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a power efficient current feedback Instrumentation Amplifier for precision bridge readout
International Conference on Electron Devices and Solid-State Circuits, 2015Co-Authors: Moaaz Ahmed, Saqib Mohamad, Amine BermakAbstract:A current-feedback Instrumentation Amplifier (CFIA) for precision bridge-readout intended for MEMs flow sensor is presented. The proposed CFIA is chopped to bring input-referred offset below 12μV and flicker-noise corner around 2mHz. Implemented in chartered 0.18μm CMOS process, the CFIA draws 250μA supply current and achieves a competitive noise efficiency factor (NEF) of 30.5. The low-power consumption is attributed to the g m /I D based design methodology adopted in designing the folded-cascode Amplifiers while considering careful trade-offs between power, thermal noise and input-referred offset.