Integration Level

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The Experts below are selected from a list of 7011 Experts worldwide ranked by ideXlab platform

Kris Myny - One of the best experts on this subject based on the ideXlab platform.

L. White - One of the best experts on this subject based on the ideXlab platform.

  • ICSM - A study of Integration testing and software regression at the Integration Level
    Proceedings. Conference on Software Maintenance 1990, 1990
    Co-Authors: H.k.n. Leung, L. White
    Abstract:

    The authors identify the common errors and faults in combining modules into a working unit. They also make practical recommendations on test selection for Integration testing and utilize these recommendations for regression testing at the Integration Level. With emphasis on reusing the previous test cases and retesting only the parts that are modified, one can reduce the testing expenses. The concept of 'firewall' is proposed to assist the tester in focusing on that part of the system where new errors may have been introduced by a correction or a design change. An experiment is presented in which an application of strategy is compared with the 'retest-all' strategy. By applying the approach for test selection, it is possible to discover all errors found by the retest-all strategy by executing only 35% of the total number of test cases. >

  • A study of Integration testing and software regression at the Integration Level
    Proceedings. Conference on Software Maintenance 1990, 1990
    Co-Authors: H.k.n. Leung, L. White
    Abstract:

    The authors identify the common errors and faults in combining modules into a working unit. They also make practical recommendations on test selection for Integration testing and utilize these recommendations for regression testing at the Integration Level. With emphasis on reusing the previous test cases and retesting only the parts that are modified, one can reduce the testing expenses. The concept of 'firewall' is proposed to assist the tester in focusing on that part of the system where new errors may have been introduced by a correction or a design change. An experiment is presented in which an application of strategy is compared with the 'retest-all' strategy. By applying the approach for test selection, it is possible to discover all errors found by the retest-all strategy by executing only 35% of the total number of test cases.

Jan Genoe - One of the best experts on this subject based on the ideXlab platform.

M. Aikawa - One of the best experts on this subject based on the ideXlab platform.

  • highly integrated three dimensional mmic technology applied to novel masterslice gaas and si mmics
    IEEE Journal of Solid-state Circuits, 1997
    Co-Authors: T. Tokumitsu, N Hirano, K Yamasaki, C Yamaguchi, Kenjiro Nishikawa, M. Aikawa
    Abstract:

    A novel three-dimensional (3-D) masterslice monolithic microwave integrated circuit (MMIC) is presented that significantly reduces turnaround time and cost for multifunction MMIC production. This MMIC incorporates an artificial ground metal for effective selection of master array elements on the wafer surface, resulting in various MMIC implementations on a master-arrayed footprint in association with thin polyimide and metal layers over it. Additionally, the 3-D miniature circuit components of less than 0.4 mm/sup 2/ in size provide a very high Integration Level. To clearly show the advantages, a 20-GHz-band receiver MMIC was implemented on a master array with 6/spl times/3 array units including a total of 36 MESFETs in a 1.78/spl times/1.78 mm area. Details of the miniature circuit components and the design, closely related to the fabrication process, are also presented. The receiver MMIC exhibited a 19-dB conversion gain with an associated 6.5-dB noise figure from 17 to 24 GHz and an Integration Level four times higher than conventional planar MMICs. This technology promises about a 90% cost reduction for MMIC because it can be similarly applied to large-scale Si wafers with the aid of an artificial ground.

  • Highly integrated three-dimensional MMIC single-chip receiver and transmitter
    1996 IEEE MTT-S International Microwave Symposium Digest, 1996
    Co-Authors: I. Toyoda, T. Tokumitsu, M. Aikawa
    Abstract:

    A three-dimensional (3D) MMIC structure with thin polyimide-film layers on wafers significantly increases the Integration Level of MMICs. We newly developed 9.2-12 GHz receiver and 9.5-14 GHz transmitter chips with 20 dB gain using 3D MMIC technology. The Integration Levels of these chips are nearly three times as high as those of conventional planar ones.

Gerwin H. Gelinck - One of the best experts on this subject based on the ideXlab platform.

  • Electrical Characterization of Flexible InGaZnO Transistors and 8-b Transponder Chip Down to a Bending Radius of 2 mm
    IEEE Transactions on Electron Devices, 2015
    Co-Authors: Ashutosh Kumar Tripathi, Kimberley Wezenberg, Kris Myny, Gerwin H. Gelinck
    Abstract:

    In this paper, we present the fabrication and characterization of highly flexible indium-gallium-zinc-oxide (IGZO)-based thin-film transistors (TFTs) and integrated circuits on a transparent and thin polymer substrate. Mechanical reliability tests are performed under bending conditions down to a bending radius of 2 mm. All the TFT parameters show only a weak dependence on mechanical strain. TFTs can withstand bending strain up to 0.75% without any significant change in the device operation. Mechanical reliability is further demonstrated to a higher TFT Integration Level by ring oscillators and 8-b transponder chips operating at a bending radius of 2 mm.