The Experts below are selected from a list of 264 Experts worldwide ranked by ideXlab platform

N.a. Touba - One of the best experts on this subject based on the ideXlab platform.

  • Observing test response of embedded Cores through surrounding logic
    1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999
    Co-Authors: P.k. Jaini, N.a. Touba
    Abstract:

    This paper addresses the problem of observing the test response of an embedded Intellectual Property Core. For the Core test set specified by the Core vendor, the logic surrounding the Core can mask errors at the output of the Core such that faults in the Core may go undetected. For Intellectual Property Cores where there is no knowledge of the internal structure of the Core (i.e., the Core is a black box), no assumptions can be made about what errors the faults in the Core may cause at the Core outputs. All possible errors at the Core outputs must be observable. Existing observation point insertion techniques (all of which are based on a fault model and require knowledge of the circuit structure) cannot be used. The conventional solution to this problem is to directly observe the Core outputs by either multiplexing them to chip pins or placing a boundary scan around the Core. This paper describes necessary and sufficient conditions (assuming no knowledge of the internal structure of the Core) for guaranteeing that all errors at the outputs of the Core can be observed through logic surrounding the Core (combinational or sequential). A systematic method for inserting a minimal set of observation points necessary for testing a Core (with either parallel or serial access) is presented.

  • ISCAS (1) - Observing test response of embedded Cores through surrounding logic
    ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999
    Co-Authors: P.k. Jaini, N.a. Touba
    Abstract:

    This paper addresses the problem of observing the test response of an embedded Intellectual Property Core. For the Core test set specified by the Core vendor, the logic surrounding the Core can mask errors at the output of the Core such that faults in the Core may go undetected. For Intellectual Property Cores where there is no knowledge of the internal structure of the Core (i.e., the Core is a black box), no assumptions can be made about what errors the faults in the Core may cause at the Core outputs. All possible errors at the Core outputs must be observable. Existing observation point insertion techniques (all of which are based on a fault model and require knowledge of the circuit structure) cannot be used. The conventional solution to this problem is to directly observe the Core outputs by either multiplexing them to chip pins or placing a boundary scan around the Core. This paper describes necessary and sufficient conditions (assuming no knowledge of the internal structure of the Core) for guaranteeing that all errors at the outputs of the Core can be observed through logic surrounding the Core (combinational or sequential). A systematic method for inserting a minimal set of observation points necessary for testing a Core (with either parallel or serial access) is presented.

Anirban Sengupta - One of the best experts on this subject based on the ideXlab platform.

  • Reusable Intellectual Property Core protection for both buyer and seller
    2018 IEEE International Conference on Consumer Electronics (ICCE), 2018
    Co-Authors: Anirban Sengupta
    Abstract:

    This paper presents a methodology for IP Core protection of CE devices from both buyer's and seller's perspective. In the presented methodology, buyer fingerprint is embedded along seller watermark during architectural synthesis phase of IP Core design. The buyer fingerprint is inserted during scheduling phase while seller watermark is implanted during register allocation phase of architectural synthesis process. The presented approach provides a robust mechanisms of IP Core protection for both buyer and seller at zero area overhead, 1.1 % latency overhead and 0.95 % design cost overhead compared to a similar approach (that provides only protection to IP seller).

  • ICCE - Reusable Intellectual Property Core protection for both buyer and seller
    2018 IEEE International Conference on Consumer Electronics (ICCE), 2018
    Co-Authors: Anirban Sengupta
    Abstract:

    This paper presents a methodology for IP Core protection of CE devices from both buyer's and seller's perspective. In the presented methodology, buyer fingerprint is embedded along seller watermark during architectural synthesis phase of IP Core design. The buyer fingerprint is inserted during scheduling phase while seller watermark is implanted during register allocation phase of architectural synthesis process. The presented approach provides a robust mechanisms of IP Core protection for both buyer and seller at zero area overhead, 1.1 % latency overhead and 0.95 % design cost overhead compared to a similar approach (that provides only protection to IP seller).

  • Guest Editorial Securing IoT Hardware: Threat Models and Reliable, Low-Power Design Solutions
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017
    Co-Authors: Anirban Sengupta, Sandip Kundu
    Abstract:

    It is well understood that for Internet of Things (IoT), security of underlying hardware is the key to safe and reliable operation. IoT service stack relies on security of network, software, and firmware, all of which, in turn, depend on functionality provided by the underlying hardware. The hardware may be compromised or attacked by multiple threat actors. The designer may create a backdoor that leaks vital information such as encryption key used in secure channel; the manufacturer may tamper the design by inserting hardware Trojans or introducing artifacts with known reliability vulnerabilities. Either of these actors may enable writing into protected memory areas that may store secure hash of trusted code base, allowing malware to boot directly on the hardware. Today’s designs integrate IP blocks from multiple vendors; manufactured, tested, and repaired by different companies spanning across the globe. Consequently, there are many entry points for the hardware to be compromised. For a trusted hardware design, protection and security of Intellectual Property Cores are of paramount importance. This special section aims to publish novel solutions for security problems related to hardware used in IoT. •Secured IoT Hardware: Induction of any form of third-party intervention in the hardware design methodology may raise grave security concern for IoT hardware. Securing IoT hardware can be in the form of protecting Intellectual Property Cores against false claim of ownership/piracy/counterfeit. The first form of security measure requires anti-piracy methodologies such as digital watermarking, hardware metering, computational forensic engineering, and obfuscation that can nullify the false claim of ownership or detect unauthorized pirated designs. The second form of threat, which is formally called “hardware Trojan,ȁ- ; is an act of deliberate insertion into a design (such as Intellectual Property Core, hardware) by a rogue designer or vendor, and also requires detection/correction strategies as a security measure. Both hardware threats discussed above may occur in any of the design abstraction levels (behavioral, register transfer, layout, etc.). Handling the threats higher in the abstraction level provides more assurance against possible attacks, however, it requires a more sophisticated approach. Further more, the level at which protective measure is applied often dictates the preprocessing or postprocessing style of the approach. These calls for novel technique that embeds hardware security measure a higher abstraction level for protection of IoT devices.•Reliable IoT Hardware: Due to multiple factors affecting reliability of hardware used in IoT devices, these devices are always at a risk of malfunctioning. For example, a manufacturer may deliberately change the width of a metal line for causing premature electromigration defect, possibly triggering a timed Trojan. Multiple trigger mechanisms may be used to attack hardware such as: 1) reducing device dimensions; 2) scaling supply voltage; and 3) modulating frequency of operation. Methodologies should incorporate techniques that provide resiliency/tolerance against such faults at higher abstraction levels to assure greater reliability from the beginning of design flow.•Low-Cost IoT Hardware: Another design aspect of hardware for IoT devices is performance and power. Consumer demand drives integration of multiple functionalities, often achieved by integrating dedicated IP Cores and general purpose processors working in tandem. This creates a unique challenge in maintaining security and integrity of data passing through various IP b

  • Hardware Security of CE Devices [Hardware Matters]
    IEEE Consumer Electronics Magazine, 2017
    Co-Authors: Anirban Sengupta
    Abstract:

    In my previous columns, I have covered various topics, including the evolution of the Intellectual Property Core industry, digital integrated circuit (IC) design flow, high-level perspectives on Intellectual Property (IP) Cores, and the transient fault resiliency of IP Cores. Though one of my previous columns focused on providing a generic cognizance about the protection of reusable IP Cores, it did not delve deep into the threat models and defense mechanisms against hardware trojans and IP piracy. This column discusses hardware security of consumer electronics (CE) devices, focusing primarily on threat models and defense mechanisms against two major attacks: hardware trojans and IP piracy.

P.k. Jaini - One of the best experts on this subject based on the ideXlab platform.

  • Observing test response of embedded Cores through surrounding logic
    1999 IEEE International Symposium on Circuits and Systems (ISCAS), 1999
    Co-Authors: P.k. Jaini, N.a. Touba
    Abstract:

    This paper addresses the problem of observing the test response of an embedded Intellectual Property Core. For the Core test set specified by the Core vendor, the logic surrounding the Core can mask errors at the output of the Core such that faults in the Core may go undetected. For Intellectual Property Cores where there is no knowledge of the internal structure of the Core (i.e., the Core is a black box), no assumptions can be made about what errors the faults in the Core may cause at the Core outputs. All possible errors at the Core outputs must be observable. Existing observation point insertion techniques (all of which are based on a fault model and require knowledge of the circuit structure) cannot be used. The conventional solution to this problem is to directly observe the Core outputs by either multiplexing them to chip pins or placing a boundary scan around the Core. This paper describes necessary and sufficient conditions (assuming no knowledge of the internal structure of the Core) for guaranteeing that all errors at the outputs of the Core can be observed through logic surrounding the Core (combinational or sequential). A systematic method for inserting a minimal set of observation points necessary for testing a Core (with either parallel or serial access) is presented.

  • ISCAS (1) - Observing test response of embedded Cores through surrounding logic
    ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999
    Co-Authors: P.k. Jaini, N.a. Touba
    Abstract:

    This paper addresses the problem of observing the test response of an embedded Intellectual Property Core. For the Core test set specified by the Core vendor, the logic surrounding the Core can mask errors at the output of the Core such that faults in the Core may go undetected. For Intellectual Property Cores where there is no knowledge of the internal structure of the Core (i.e., the Core is a black box), no assumptions can be made about what errors the faults in the Core may cause at the Core outputs. All possible errors at the Core outputs must be observable. Existing observation point insertion techniques (all of which are based on a fault model and require knowledge of the circuit structure) cannot be used. The conventional solution to this problem is to directly observe the Core outputs by either multiplexing them to chip pins or placing a boundary scan around the Core. This paper describes necessary and sufficient conditions (assuming no knowledge of the internal structure of the Core) for guaranteeing that all errors at the outputs of the Core can be observed through logic surrounding the Core (combinational or sequential). A systematic method for inserting a minimal set of observation points necessary for testing a Core (with either parallel or serial access) is presented.

R. Kinkead - One of the best experts on this subject based on the ideXlab platform.

  • Semiconductor IP Core for ultra low power MPEG-4 video decode in system-on-silicon
    2003 IEEE International Conference on Acoustics Speech and Signal Processing 2003. Proceedings. (ICASSP '03)., 2003
    Co-Authors: J. Dunlop, A. Simpson, S. Masud, M. Wylie, J. Cochrane, R. Kinkead
    Abstract:

    An ultra low power, hardware accelerated architecture based semiconductor Intellectual Property Core for MPEG-4 has been developed. This encompasses the simple profile of the video decoding algorithm. The Core can provide motion picture quality video at up to CIF resolution. The implementation is based on the application of hardware acceleration of compute-intensive operations with an embedded RISC processor acting purely as a host controller. The architecture comprises custom hardware designs for lookup table decoders, bitstream parsing, discrete cosine transforms, motion compensation and colour space conversion. The hardware-software co-design approach results in high efficiency in both area and performance. The design has been validated on an FPGA-based development board with an LCD panel for visual demonstration of real-time decoded streaming video sequences. This MPEG-4 video decoder Core has been ported to 130 nm ASIC technology using system-level integration techniques where the power dissipation is around 10 mWatts. The design is ideally suited to high-volume system-on-chip solutions for a wide range of wireless multimedia communication applications.

Dhiraj K. Pradhan - One of the best experts on this subject based on the ideXlab platform.

  • A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection
    IEEE Transactions on Reliability, 2015
    Co-Authors: Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan
    Abstract:

    On-chip security is an emerging challenge in the design of embedded systems with Intellectual Property (IP) Cores. Traditionally this challenge is addressed using ad hoc design techniques with separate design objectives of secure design for testability (DfT), and IP Core protection. However, in this paper, we will argue that such design approaches can incur high costs. Underpinning this argument, we propose a novel design methodology, called Secure TEst and IP Core Protection (STEP), which aims to address the joint objective of IP Core protection and secure testing. To ensure that this objective is achieved at a low cost, the STEP design methodology employs common key integrated hardware. This hardware is incorporated in the system through an automated design conversion technique, which can be easily merged into the electronic design automation (EDA) tool chain. We evaluate the effectiveness of our proposed design methodology considering various implementations of advanced encryption standard (AES) systems as case studies. We show that our proposed design methodology benefits from design automation with high security, and protection at the cost of low area, and power consumption overheads, when compared with traditional design methodologies.