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D. Bauza - One of the best experts on this subject based on the ideXlab platform.

  • on the si sio2 Interface Trap time constant distribution in metal oxide semiconductor transistors
    Journal of Applied Physics, 2005
    Co-Authors: Y. Maneglia, F Rahmoune, D. Bauza
    Abstract:

    The reliability of a charge pumping (CP) technique proposed recently, which allows the extraction of the Si–SiO2 Interface Trap concentration profiles in metal-oxide-semiconductor transistors, from fast to slow Traps, is discussed. The shape of the Trap concentration profiles measured, the values of the Trap cross section extracted, and the integration of the Trap profiles, which should give the Interface Trap density obtained using the conventional CP technique, are discussed with regard to the Trap filling function variation and to surface-potential fluctuations. Then, the influence, on these profiles, of both carrier emission, which is neglected in the model used for calculating the profiles, and of the source and drain regions (S/D-R) of the devices, where the threshold and flatband voltages are different from those in the central region of the channel, is investigated. It is shown that carrier emission does not impact on the Trap profiles and that the Trap time constant distribution measured does not...

  • Extraction of Si-SiO2 Interface Trap densities in MOS structures with ultrathin oxides
    IEEE Electron Device Letters, 2002
    Co-Authors: D. Bauza
    Abstract:

    Si-SiO/sub 2/ Interface Trap densities can be measured in MOS structures with ultrathin oxides using charge pumping (CP) and small gate pulses. This presents three decisive advantages with respect to the conventional large gate voltage swing approach. First, the extraction is simple as carrier emission does not contribute to the CP signal so that the CP current magnitude directly reflects the Interface Trap density. Second, the tunneling current is strongly reduced allowing a more easy extraction of the CP signal and third, such a reduction prevents the insulator and the insulator-silicon Interface from any degradation. By doing so, Si-SiO/sub 2/ Interface Trap densities are measured in MOSFETs with oxides which are 1.8 and 1.3 nm thick.

  • Evolution of the Si-SiO/sub 2/ Interface Trap characteristics with Fowler-Nordheim injection
    ICMTS 1999. Proceedings of 1999 International Conference on Microelectronic Test Structures (Cat. No.99CH36307), 1999
    Co-Authors: Y. Maneglia, D. Bauza
    Abstract:

    Using a recently proposed method based on charge pumping measurements which allows the extraction of the Si-SiO/sub 2/ Interface Trap depth concentration profiles, the Trap parameters are studied as a function of Fowler-Nordheim injection. As the stress proceeds, the Interface Trap layer extends deeper in the direction of the oxide depth, the Trap density in the oxide seems to increase faster than that at the Interface and the Trap capture cross-sections strongly increase. This induces deeper penetration of the carriers into the oxide depth and a larger contribution of the so-called slow Traps to the device electrical properties. This can be viewed as an extension of the Si-SiO/sub 2/ Interface in the direction of the oxide depth.

K.f. Lo - One of the best experts on this subject based on the ideXlab platform.

  • Energy dependence of Interface Trap density-investigated by the DCIV method [MOSFETs]
    Proceedings of the 1999 7th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.99TH8394), 1999
    Co-Authors: M.f. Li, K.f. Lo
    Abstract:

    Based on DC current-voltage (DCIV) measurements, a new method is proposed for evaluation of the energy dependence of Interface Trap density in deep sub-/spl mu/m MOSFETs. An emitter forward bias V/sub eb/ dependent parameter N/sub EFF/(V/sub eb/) is introduced and is calculated from the magnitude of the DCIV spectrum peak. The energy dependence of the Interface Trap density can be acquired from comparing the experimental and theoretical N/sub EFF/(V/sub eb/) curves using least squares optimisation. The method is illustrated with a 0.4 /spl mu/m channel length pMOSFET subject to Fowler-Nordheim stressing.

  • A comparison of Interface Trap generation by Fowler-Nordheim electron injection and hot-hole injection using the DCIV method
    Proceedings of the 1999 7th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.99TH8394), 1999
    Co-Authors: K.h. Ng, M.f. Li, Y.d. He, W.k. Chim, K.f. Lo
    Abstract:

    We report on the different behaviours of Interface Trap generation caused by Fowler-Nordheim (F-N) electron injection and by hot-hole injection using the direct current current-voltage (DCIV) method. The hole-electron ratio of the gate current under hot-hole injection conditions is quantified. The study shows that the efficiency of hole-induced Interface Trap generation is about 150 times that of electron-induced Interface Trap generation. Furthermore, Interface Trap generation by both hole and electron injections obey a power-law relation with injected fluence. The hot-hole injection is observed to have a smaller power exponent than F-N electron injection.

  • Interface Trap generation by FN injection under dynamic oxide field stress
    IEEE Transactions on Electron Devices, 1998
    Co-Authors: T.p. Chen, Stella Li, S. Fung, K.f. Lo
    Abstract:

    Interface Trap generation under dynamic (bipolar and unipolar) and dc oxide field stress has been investigated with the charge pumping technique. It is observed that regardless of stress type, whether dc or dynamic (bipolar or unipolar), and the polarity of stress voltage, Interface Trap generation starts to occur at the voltage at which Fowler-Nordheim (FN) tunneling through the oxide starts to build up. For positive voltage, Interface Trap generation is attributed to the recombination of Trapped holes with electrons and to the bond breaking by the hydrogen (H and H/sup +/) released during stressing. For negative voltage, in addition to these two mechanisms, the bond breaking by energetic electrons may also contribute to Interface Trap generation. The frequency dependence of Interface Trap generation is also investigated. Interface Trap generation is independent of stressing frequency for unipolar stress but it shows a frequency dependence for bipolar stress.

  • Post-stress Interface Trap generation induced by oxide-field stress with FN injection
    IEEE Transactions on Electron Devices, 1998
    Co-Authors: T.p. Chen, Stella Li, S. Fung, C.d. Beling, K.f. Lo
    Abstract:

    Interface Trap generation in nMOS transistors during both stressing and post-stress periods under the conditions of oxide field (dynamic and dc) stress with FN injection is investigated with charge pumping technique. In contrast to the post-stress Interface Trap generation induced by hot carrier stress which is a logarithmical function of post-stress time, the post-stress Interface Trap generation induced by oxide-field stress with FN injection first increases with post-stress time but then becomes saturated. The mechanisms for the Interface Trap generation in both stressing and post-stress periods are described.

Yun Seop Yu - One of the best experts on this subject based on the ideXlab platform.

  • metal oxide graphene field effect transistor Interface Trap density extraction model
    Beilstein Journal of Nanotechnology, 2016
    Co-Authors: Faraz Najam, Yun Seop Yu
    Abstract:

    A simple to implement model is presented to extract Interface Trap density of graphene field effect transistors. The presence of Interface Trap states detrimentally affects the device drain current-gate voltage relationship Ids-Vgs. At the moment, there is no analytical method available to extract the Interface Trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the Interface Trap distribution of MOGFET devices making use of available experimental capacitance-gate voltage Ctot-Vgs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the Interface Trap distribution of 2 experimental devices. Device parameters calculated using the extracted Interface Trap distribution from the model, including surface potential, Interface Trap charge and Interface Trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by Trap charge. Other models ignore the effect of Trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

  • Gate All Around Metal Oxide Field Transistor: Surface Potential Calculation Method including Doping and Interface Trap Charge and the Effect of Interface Trap Charge on Subthreshold Slope
    Journal of Semiconductor Technology and Science, 2013
    Co-Authors: Faraz Najam, Yun Seop Yu
    Abstract:

    An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both Interface Trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of Interface Trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of Interface Trap charge on device SS performance are investigated.

  • Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model
    IEEE Transactions on Electron Devices, 2013
    Co-Authors: Faraz Najam, Yun Seop Yu, Jong Seung Hwang, Sung Woo Hwang
    Abstract:

    Si/SiO2 Interface Trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the Interface chemistry of conventional gatestack ( Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on Interface Trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with Interface Trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of Interface Trap charge and surface potential to reproduce experimental current-voltage characteristics.

Faraz Najam - One of the best experts on this subject based on the ideXlab platform.

  • metal oxide graphene field effect transistor Interface Trap density extraction model
    Beilstein Journal of Nanotechnology, 2016
    Co-Authors: Faraz Najam, Yun Seop Yu
    Abstract:

    A simple to implement model is presented to extract Interface Trap density of graphene field effect transistors. The presence of Interface Trap states detrimentally affects the device drain current-gate voltage relationship Ids-Vgs. At the moment, there is no analytical method available to extract the Interface Trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the Interface Trap distribution of MOGFET devices making use of available experimental capacitance-gate voltage Ctot-Vgs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the Interface Trap distribution of 2 experimental devices. Device parameters calculated using the extracted Interface Trap distribution from the model, including surface potential, Interface Trap charge and Interface Trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by Trap charge. Other models ignore the effect of Trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

  • Gate All Around Metal Oxide Field Transistor: Surface Potential Calculation Method including Doping and Interface Trap Charge and the Effect of Interface Trap Charge on Subthreshold Slope
    Journal of Semiconductor Technology and Science, 2013
    Co-Authors: Faraz Najam, Yun Seop Yu
    Abstract:

    An explicit surface potential calculation method of gate-all-around MOSFET (GAAMOSFET) devices which takes into account both Interface Trap charge and varying doping levels is presented. The results of the method are extensively verified by numerical simulation. Results from the model are used to find qualitative and quantitative effect of Interface Trap charge on subthreshold slope (SS) of GAAMOSFET devices. Further, design constraints of GAAMOSFET devices with emphasis on the effect of Interface Trap charge on device SS performance are investigated.

  • Interface Trap Density of Gate-All-Around Silicon Nanowire Field-Effect Transistors With TiN Gate: Extraction and Compact Model
    IEEE Transactions on Electron Devices, 2013
    Co-Authors: Faraz Najam, Yun Seop Yu, Jong Seung Hwang, Sung Woo Hwang
    Abstract:

    Si/SiO2 Interface Trap charge distribution of cylindrical cross-sectioned gate-all-around silicon nanowire field-effect transistor is extracted by using three-dimensional simulation. While the Interface chemistry of conventional gatestack ( Si/SiO2 polysilicon) in conventional planar devices is well documented, not much work is available on Interface Trap distribution Dit of alternate gatestacks (gatestacks employing alternate gate materials) in silicon nanowire MOSFET devices. Furthermore, a compact drain current model with Interface Trap charge parameter is presented. The model is based on gradual channel approximation and uses self-consistent calculation of Interface Trap charge and surface potential to reproduce experimental current-voltage characteristics.

H E Maes - One of the best experts on this subject based on the ideXlab platform.

  • on the correct extraction of Interface Trap density of mos devices with high mobility semiconductor substrates
    IEEE Transactions on Electron Devices, 2008
    Co-Authors: Koen Martens, Chi On Chui, Guy Brammertz, B De Jaeger, Duygu Kuzum, Marc Meuris, Marc Heyns, Tejas Krishnamohan, K C Saraswat, H E Maes
    Abstract:

    ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate Interface Trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the Interface Trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used Interface Trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

  • Post-stress Interface Trap generation: a new hot-carrier induced degradation phenomenon in passivated n-channel MOSFET's
    30th Annual Proceedings Reliability Physics 1992, 1992
    Co-Authors: E. De Schrijver, P Heremans, G Groeseneken, R. Bellens, H E Maes
    Abstract:

    Passivated n-channel MOSFETs can show significant increases in Interface Trap density after termination of hot carrier stress. The dependence of this poststress Interface Trap generation mechanism on various parameters was investigated. A simple model based on the generation of both positive and neutral hydrogen by deTrapped holes injected during stress can account for all observed phenomena. For accelerated lifetime experiments under AC conditions for which hole injection occurs, an apparently non-quasistatic behavior was observed that can be readily explained by this mechanism. Prediction of device lifetime under AC conditions, based solely on DC experiments, is then straightforward.

  • spectroscopic charge pumping a new procedure for measuring Interface Trap distributions on mos transistors
    IEEE Transactions on Electron Devices, 1991
    Co-Authors: G Van Den Bosch, G Groeseneken, P Heremans, H E Maes
    Abstract:

    An approach to the application of the charge pumping technique is proposed as a tool for the measurement of Interface Trap energy distributions in small area MOS transistors. The new approach is spectroscopic in nature, i.e., only one energy window is defined, and forced to move through the bandgap by changing the sample temperature. This method has the advantages of addressing a larger part of the bandgap as compared to the classical approach, of reducing the complication in the processing of the data, and of yielding information about the hole and electron capture cross sections separately. Experiments performed on both n-channel and p-channel MOS transistors reveal that, in the temperature (energy) range studied, the Interface-Trap distribution is slowly varying with energy and that the Trap capture cross section is nearly constant over energy and temperature. >