The Experts below are selected from a list of 312 Experts worldwide ranked by ideXlab platform

M.a. Breuer - One of the best experts on this subject based on the ideXlab platform.

  • VTS - Test generation for maximizing ground bounce for Internal Circuitry with reconvergent fan-outs
    Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 2001
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Due to technology scaling and increasing clock rate, problems due to noise effects lead to an increase in design and test efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and effectively generating two vector tests to produce the maximum ground bounce in a circuit. We have developed a branch and bound procedure that can find a good quality test for maximum ground bounce in a rather short time. Comparison of results with SPICE simulations confirms the quality of tests obtained by our procedure.

  • Test generation for ground bounce in Internal logic Circuitry
    Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 1999
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce in Internal Circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in Internal Circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.

  • VTS - Test generation for ground bounce in Internal logic Circuitry
    Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 1999
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce in Internal Circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in Internal Circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.

  • analysis of ground bounce in deep sub micron circuits
    VLSI Test Symposium, 1997
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce occurs in integrated circuits and can cause signal distortion and increase gate delay. This can result in improper circuit operation. In the past, the switching of input/output buffers was the primary cause of the ground bounce. In designs employing deep sub-micron technology high operating frequency, and short rise/fall times, ground bounce due to switching in Internal Circuitry becomes a potential problem. In this paper experiments based on realistic assumptions are performed to explore the properties of ground bounce. Experiments indicate that (1) ground bounce is generated in gates, irrespective of whether outputs switch from 0 to 1 or from 1 to 0, (2) ground bounce is reduced when the load capacitance increases, and (3) ground bounce decreases when the number of gates that switch is held constant while the number of gates that don't switch increases. These conclusions are different from what has been found when input/output buffers switch and lead to new design, verification and test issues.

  • VTS - Analysis of ground bounce in deep sub-micron circuits
    Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125), 1997
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce occurs in integrated circuits and can cause signal distortion and increase gate delay. This can result in improper circuit operation. In the past, the switching of input/output buffers was the primary cause of the ground bounce. In designs employing deep sub-micron technology high operating frequency, and short rise/fall times, ground bounce due to switching in Internal Circuitry becomes a potential problem. In this paper experiments based on realistic assumptions are performed to explore the properties of ground bounce. Experiments indicate that (1) ground bounce is generated in gates, irrespective of whether outputs switch from 0 to 1 or from 1 to 0, (2) ground bounce is reduced when the load capacitance increases, and (3) ground bounce decreases when the number of gates that switch is held constant while the number of gates that don't switch increases. These conclusions are different from what has been found when input/output buffers switch and lead to new design, verification and test issues.

Yi-shing Chang - One of the best experts on this subject based on the ideXlab platform.

  • VTS - Test generation for maximizing ground bounce for Internal Circuitry with reconvergent fan-outs
    Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 2001
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Due to technology scaling and increasing clock rate, problems due to noise effects lead to an increase in design and test efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and effectively generating two vector tests to produce the maximum ground bounce in a circuit. We have developed a branch and bound procedure that can find a good quality test for maximum ground bounce in a rather short time. Comparison of results with SPICE simulations confirms the quality of tests obtained by our procedure.

  • Test generation for maximizing ground bounce for Internal Circuitry with reconvergent fan-outs
    Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 2001
    Co-Authors: Yi-shing Chang, S. Gupta, M. Breuer
    Abstract:

    Due to technology scaling and increasing clock rate, problems due to noise effects lead to an increase in design and test efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and effectively generating two vector tests to produce the maximum ground bounce in a circuit. We have developed a branch and bound procedure that can find a good quality test for maximum ground bounce in a rather short time. Comparison of results with SPICE simulations confirms the quality of tests obtained by our procedure.

  • Test generation for ground bounce in Internal logic Circuitry
    Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 1999
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce in Internal Circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in Internal Circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.

  • VTS - Test generation for ground bounce in Internal logic Circuitry
    Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 1999
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce in Internal Circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in Internal Circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.

  • analysis of ground bounce in deep sub micron circuits
    VLSI Test Symposium, 1997
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce occurs in integrated circuits and can cause signal distortion and increase gate delay. This can result in improper circuit operation. In the past, the switching of input/output buffers was the primary cause of the ground bounce. In designs employing deep sub-micron technology high operating frequency, and short rise/fall times, ground bounce due to switching in Internal Circuitry becomes a potential problem. In this paper experiments based on realistic assumptions are performed to explore the properties of ground bounce. Experiments indicate that (1) ground bounce is generated in gates, irrespective of whether outputs switch from 0 to 1 or from 1 to 0, (2) ground bounce is reduced when the load capacitance increases, and (3) ground bounce decreases when the number of gates that switch is held constant while the number of gates that don't switch increases. These conclusions are different from what has been found when input/output buffers switch and lead to new design, verification and test issues.

Rik W. De Doncker - One of the best experts on this subject based on the ideXlab platform.

  • Nodal-reduced modeling of three-phase dual-active bridge converters for EMTP-type simulations
    2017 IEEE 26th International Symposium on Industrial Electronics (ISIE), 2017
    Co-Authors: Amir Arasteh, Antonello Monti, Arne Hinz, Rik W. De Doncker
    Abstract:

    Modeling the terminal behavior of power system components in transient condition is of great necessity for system-level simulations of future DC grids. One vital component in DC grids are power electronic converters. Therefore, efficient models of power electronic converters, which model their terminal behavior, are needed for transient system-level simulations. In this paper, an approach for eliminating all Internal electrical nodes of power electronic converters in EMTP-type simulations is applied on the three-phase Dual-Active Bridge DC-DC converter. The presented modeling approach maintains the switching dynamics as well as the dynamics caused by the Internal Circuitry at the terminals of the converter. Furthermore, this modeling approach reduces the number of electrical nodes in EMTP-type simulations. This leads to a reduction of the computational burden when simulating extensive DC grids with a large number of power electronic converters. The presented nodal-reduced model enables the efficient system-level simulation of future DC grids using EMTP-type simulators.

  • IECON - Nodal-reduced modeling of single-phase Dual-Active Bridge converters for EMTP-type simulations
    IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society, 2016
    Co-Authors: Arne Hinz, Antonello Monti, Rik W. De Doncker
    Abstract:

    Transient system-level simulations of future DC grids require modeling the behavior at the terminals of the power system's components, and thus also of power converters. The Internal electrical variables of the power electronic devices are not relevant in such simulations. Based on this, this paper presents an approach for eliminating all the Internal electrical nodes of a single-phase Dual-Active Bridge DC-DC converter for EMTP-type simulations. Nonetheless, the switching dynamics at the terminals of the converter are maintained, while the dynamic effects of the converter-Internal Circuitry like transformer and capacitors are accounted for. By reducing all Internal nodes of the converter model, the computational burden is reduced, which is especially important for system-level simulations of large grids. The approach presented here is a first step towards a similar implementation for the three-phase Dual-Active Bridge DC-DC converter topology, a promising converter topology for future DC grids.

  • Nodal-reduced modeling of single-phase Dual-Active Bridge converters for EMTP-type simulations
    IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society, 2016
    Co-Authors: Arne Hinz, Antonello Monti, Rik W. De Doncker
    Abstract:

    Transient system-level simulations of future DC grids require modeling the behavior at the terminals of the power system's components, and thus also of power converters. The Internal electrical variables of the power electronic devices are not relevant in such simulations. Based on this, this paper presents an approach for eliminating all the Internal electrical nodes of a single-phase Dual-Active Bridge DC-DC converter for EMTP-type simulations. Nonetheless, the switching dynamics at the terminals of the converter are maintained, while the dynamic effects of the converter-Internal Circuitry like transformer and capacitors are accounted for. By reducing all Internal nodes of the converter model, the computational burden is reduced, which is especially important for system-level simulations of large grids. The approach presented here is a first step towards a similar implementation for the three-phase Dual-Active Bridge DC-DC converter topology, a promising converter topology for future DC grids.

S.k. Gupta - One of the best experts on this subject based on the ideXlab platform.

  • VTS - Test generation for maximizing ground bounce for Internal Circuitry with reconvergent fan-outs
    Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 2001
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Due to technology scaling and increasing clock rate, problems due to noise effects lead to an increase in design and test efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and effectively generating two vector tests to produce the maximum ground bounce in a circuit. We have developed a branch and bound procedure that can find a good quality test for maximum ground bounce in a rather short time. Comparison of results with SPICE simulations confirms the quality of tests obtained by our procedure.

  • Test generation for ground bounce in Internal logic Circuitry
    Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 1999
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce in Internal Circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in Internal Circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.

  • VTS - Test generation for ground bounce in Internal logic Circuitry
    Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 1999
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce in Internal Circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in Internal Circuitry is proposed. Based on this model an algorithm for generating test patterns that maximize ground bounce in combinational logic is presented. Our algorithm is also applicable to other test problems such as delay testing in the presence of excessive ground bounce.

  • analysis of ground bounce in deep sub micron circuits
    VLSI Test Symposium, 1997
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce occurs in integrated circuits and can cause signal distortion and increase gate delay. This can result in improper circuit operation. In the past, the switching of input/output buffers was the primary cause of the ground bounce. In designs employing deep sub-micron technology high operating frequency, and short rise/fall times, ground bounce due to switching in Internal Circuitry becomes a potential problem. In this paper experiments based on realistic assumptions are performed to explore the properties of ground bounce. Experiments indicate that (1) ground bounce is generated in gates, irrespective of whether outputs switch from 0 to 1 or from 1 to 0, (2) ground bounce is reduced when the load capacitance increases, and (3) ground bounce decreases when the number of gates that switch is held constant while the number of gates that don't switch increases. These conclusions are different from what has been found when input/output buffers switch and lead to new design, verification and test issues.

  • VTS - Analysis of ground bounce in deep sub-micron circuits
    Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125), 1997
    Co-Authors: Yi-shing Chang, S.k. Gupta, M.a. Breuer
    Abstract:

    Ground bounce occurs in integrated circuits and can cause signal distortion and increase gate delay. This can result in improper circuit operation. In the past, the switching of input/output buffers was the primary cause of the ground bounce. In designs employing deep sub-micron technology high operating frequency, and short rise/fall times, ground bounce due to switching in Internal Circuitry becomes a potential problem. In this paper experiments based on realistic assumptions are performed to explore the properties of ground bounce. Experiments indicate that (1) ground bounce is generated in gates, irrespective of whether outputs switch from 0 to 1 or from 1 to 0, (2) ground bounce is reduced when the load capacitance increases, and (3) ground bounce decreases when the number of gates that switch is held constant while the number of gates that don't switch increases. These conclusions are different from what has been found when input/output buffers switch and lead to new design, verification and test issues.

Han-woong Choi - One of the best experts on this subject based on the ideXlab platform.

  • ICEIC - Wireless DC power Generator for Passive RFID by using Cockcroft-Walton Voltage Multiplier in CMOS 0.18um Technology
    2019 International Conference on Electronics Information and Communication (ICEIC), 2020
    Co-Authors: Jae-hyeok Song, Sun-kyu Choi, Han-woong Choi
    Abstract:

    This paper presents a DC generator for passive RFID tag based on Cockcroft-Walton voltage multiplier topology. Generator has number of voltage multipliers in parallel. It includes bandgap-reference and regulator to create stably DC voltage to operate the tag's Internal Circuitry. And it has limiter circuit to prevent damage to the Internal circuit when a strong signal is received. This DC generator designed to operate at UHF 900MHz and produces an output of about 1.8V for 30k-ohm when 0dBm intensity signal is received.

  • Wireless DC power Generator for Passive RFID by using Cockcroft-Walton Voltage Multiplier in CMOS 0.18um Technology
    2019 International Conference on Electronics Information and Communication (ICEIC), 2019
    Co-Authors: Jae-hyeok Song, Sun-kyu Choi, Han-woong Choi
    Abstract:

    This paper presents a DC generator for passive RFID tag based on Cockcroft-Walton voltage multiplier topology. Generator has number of voltage multipliers in parallel. It includes bandgap-reference and regulator to create stably DC voltage to operate the tag's Internal Circuitry. And it has limiter circuit to prevent damage to the Internal circuit when a strong signal is received. This DC generator designed to operate at UHF 900MHz and produces an output of about 1.8V for 30k-ohm when 0dBm intensity signal is received.