The Experts below are selected from a list of 169005 Experts worldwide ranked by ideXlab platform
Krishna Shenai - One of the best experts on this subject based on the ideXlab platform.
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Investigation of the short-Circuit Performance of an IGBT
IEEE Transactions on Electron Devices, 1998Co-Authors: Malay Trivedi, Krishna ShenaiAbstract:This paper reports the internal dynamics of insulated gate bipolar transistors (IGBT's) under short-Circuit switching conditions. Short-Circuit Performance of IGBT's has been studied in detail with the aid of extensive measurements and numerical simulations. An advanced two-dimensional (2-D) mixed device and Circuit simulator that incorporates the self-heating mechanism has been employed to examine IGBT behavior under short-Circuit stress. Latch-up free punchthrough IGBT has been examined. It is shown that hot-spot generation due to current crowding and impact ionization is the cause of breakdown of an IGBT under short-Circuit switching.
Jawad Faiz - One of the best experts on this subject based on the ideXlab platform.
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a new multi winding traction transformer equivalent Circuit for short Circuit Performance analysis
International Transactions on Electrical Energy Systems, 2014Co-Authors: Davood Azizian, Mehdi Vakilian, Jawad FaizAbstract:SUMMARY Current and force calculations in different short-Circuit conditions are required for short-Circuit Performance analysis of a multi-winding traction transformer which is one of the most important requirements in its design process. This paper extends the available low-frequency three-winding star equivalent Circuits to develop a novel equivalent Circuit for the four-winding traction transformers. The leakage inductances of the traction transformer are determined and employed to calculate the parameters of this developed star model. It is shown that the star equivalent Circuit is a valid and appropriate model to simulate the steady-state and dynamic Performance of the traction transformer under different short-Circuit conditions. To analyze the short-Circuit Performance of the transformer, the short-Circuit currents (simulated by the introduced model) are employed to compute the electromagnetic forces for a typical dry-type traction transformer. The analytical and numerical methods are used for short-Circuit force calculations, and those results are compared against each other. Copyright © 2012 John Wiley & Sons, Ltd.
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A new multi‐winding traction transformer equivalent Circuit for short‐Circuit Performance analysis
International Transactions on Electrical Energy Systems, 2012Co-Authors: Davood Azizian, Mehdi Vakilian, Jawad FaizAbstract:SUMMARY Current and force calculations in different short-Circuit conditions are required for short-Circuit Performance analysis of a multi-winding traction transformer which is one of the most important requirements in its design process. This paper extends the available low-frequency three-winding star equivalent Circuits to develop a novel equivalent Circuit for the four-winding traction transformers. The leakage inductances of the traction transformer are determined and employed to calculate the parameters of this developed star model. It is shown that the star equivalent Circuit is a valid and appropriate model to simulate the steady-state and dynamic Performance of the traction transformer under different short-Circuit conditions. To analyze the short-Circuit Performance of the transformer, the short-Circuit currents (simulated by the introduced model) are employed to compute the electromagnetic forces for a typical dry-type traction transformer. The analytical and numerical methods are used for short-Circuit force calculations, and those results are compared against each other. Copyright © 2012 John Wiley & Sons, Ltd.
Shinsuke Harada - One of the best experts on this subject based on the ideXlab platform.
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Superior Short-Circuit Performance of SiC Superjunction MOSFET
2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), 2020Co-Authors: Masakazu Okada, Shinya Kyogoku, Teruaki Kumazawa, Jun Saito, Tadao Morimoto, Manabu Takei, Shinsuke HaradaAbstract:This study demonstrated the short-Circuit Performance of 1.2 kV-class silicon carbide (SiC) trench-gate superjunction MOSFET (SJ-UMOSFET) through experiments and numerical simulation. The SJ structure showed a substantially improved trade-off between specific on-resistance and short-Circuit capability when compared with a conventional UMOSFET, especially at a high temperature (175°C), owing to the low temperature coefficient of the specific on-resistance. Furthermore, the electro-thermal simulation showed that the SJ-UMOSFET exhibited a larger distance from an internal hot spot to the source metal contact than the UMOSFET; this increase in distance contributed to the improved short-Circuit capability demonstrated in the experiment.
Linda Milor - One of the best experts on this subject based on the ideXlab platform.
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Impact on Circuit Performance of deterministic within-die variation in nanoscale semiconductor manufacturing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006Co-Authors: Munkang Choi, Linda MilorAbstract:As semiconductor technology advances into the nanoscale era and more functional blocks are added into systems-on-chip, the interface between Circuit design and manufacturing is becoming blurred. An increasing number of features, traditionally ignored by designers, are influencing both Circuit Performance and yield. As a result, design tools need to incorporate new factors. One important source of Circuit-Performance degradation comes from deterministic within-die variation from lithography imperfections and Cu-interconnect chemical-mechanical polishing (CMP). To determine how these within-die variations impact Circuit Performance, we need a new analysis tool. Thus, we have proposed a methodology to involve layout-dependent within-die variations in static timing analysis. Our methodology combines a set of scripts and commercial tools to analyze a full chip. The tool has been applied to analyze delay of ISCAS85 benchmark Circuits in the presence of imperfect lithography and CMP variation
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characterization of spatial intrafield gate cd variability its impact on Circuit Performance and spatial mask level correction
IEEE Transactions on Semiconductor Manufacturing, 2004Co-Authors: Michael Orshansky, Linda Milor, Chenming HuAbstract:The authors present a comprehensive characterization method applied to the study of the state-of-the-art 18-/spl mu/m CMOS process. Statistical characterization of gate CD reveals a large spatial intrafield component, strongly dependent on the local layout patterns. The authors describe the statistical analysis of this data and demonstrate the need for such comprehensive characterization. They describe the experimental setup of the novel measurement-based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate Circuit modeling and statistical design for increased Performance and yield. Characterization is based upon an inexpensive electrically based measurement technique. A rigorous statistical analysis of the impact of intrafield variability on Circuit Performance is undertaken. They show that intrafield CD variation has a significant detrimental effect on the overall Circuit Performance that may be as high as 25%. Moreover, they demonstrate that the spatial component of gate CD variability, rather than the proximity-dependent component, is predominantly responsible for speed degradation. In order to reduce the degradation of Circuit Performance and yield, the authors propose a mask-level spatial gate CD correction algorithm to reduce the intrafield and overall variability and provide an analytical model to evaluate the effectiveness of correction for variance reduction. They believe that potentially significant benefits can be achieved through implementation of this compensation technique in the production environment.
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Simulation of Lithography-caused Gate Length and Interconnect Linewidth Variational Impact on Circuit Performance in Nanoscale Semiconductor Manufacturing
Simulation of Semiconductor Processes and Devices 2004, 2004Co-Authors: Munkang Choi, Cheng Jia, Linda MilorAbstract:As the critical dimension (CD) is scaled into nanometer dimensions, operating frequencies exceed a gigahertz, and more functional blocks are added into systems on chip (SoC), interconnect has become a bottleneck in achieving the system Performance [1]. In addition, scaling increases the impact of systematic intra-die CD variation (gate and metal linewidth variations) and this variation interacts with the Circuit design by degrading Circuit speed [2]. One major source of CD variation is the optical lithography process [3]. To determine how the lithography variation impacts Circuit Performance, this paper introduces a method to incorporate the lithographycaused interconnect linewidth variation in timing simulation. ISCAS benchmark Circuits are used to evaluate the Circuit Performance impact of each optical effect.
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Simulation of the Circuit Performance impact of lithography in nanoscale semiconductor manufacturing
International Conference on Simulation of Semiconductor Processes and Devices 2003. SISPAD 2003., 2003Co-Authors: Munkang Choi, Linda Milor, L. CapodieciAbstract:With nanoscale semiconductor technology, Circuit Performance is increasingly influenced by details of the manufacturing process. An increasing number of manufacturing features, which are not included in standard design tools, affect both Circuit Performance and yield. One source of Circuit Performance degradation is lithography imperfections. Therefore, we need to simulate how lithography imperfections impact Circuit Performance. Such imperfections include the proximity effect, lens aberrations, and flare. These imperfections in lithography impact Circuit timing. This paper introduces a method to incorporate the proximity effect, lens aberrations, and flare in timing simulation. Our method involves expanding and revising the cell library by considering optical effects. ISCAS benchmark Circuits are used to evaluate the Circuit Performance impact of each optical effect.
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Characterization of spatial CD variability, spatial mask-level correction, and improvement of Circuit Performance
Optical Microlithography XIII, 2000Co-Authors: Michael Orshansky, Linda Milor, Michael H. Brodsky, Ly Nguyen, Gene Hill, Yeng-kaung PengAbstract:Statistical characterization of gate CD variability of a production CMOS process reveals a large spatial intra-field component, strongly dependent on the local layout patterns. We present a novel measurement based characterization approach that is capable of capturing all the relevant CD variation patterns necessary for accurate Circuit modeling and statistical design. A rigorous analysis of the impact of intra-field variability on Circuit Performance is undertaken. We show that intra-field CD variation has a significant detrimental effect on the overall Circuit Performance by reducing the average speed by up to 20 percent. We derive a model quantitatively relating intra- field CD variance delay degradation. We propose a mask-level spatial gate CD correction algorithm to reduce the intra- field and overall variability, resulting in Circuit Performance improvement, and provide an analytical model to evaluate the effectiveness of correction for variance reduction.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
Malay Trivedi - One of the best experts on this subject based on the ideXlab platform.
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Investigation of the short-Circuit Performance of an IGBT
IEEE Transactions on Electron Devices, 1998Co-Authors: Malay Trivedi, Krishna ShenaiAbstract:This paper reports the internal dynamics of insulated gate bipolar transistors (IGBT's) under short-Circuit switching conditions. Short-Circuit Performance of IGBT's has been studied in detail with the aid of extensive measurements and numerical simulations. An advanced two-dimensional (2-D) mixed device and Circuit simulator that incorporates the self-heating mechanism has been employed to examine IGBT behavior under short-Circuit stress. Latch-up free punchthrough IGBT has been examined. It is shown that hot-spot generation due to current crowding and impact ionization is the cause of breakdown of an IGBT under short-Circuit switching.