The Experts below are selected from a list of 18 Experts worldwide ranked by ideXlab platform
Sachin S. Sapatnekar - One of the best experts on this subject based on the ideXlab platform.
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Thermal Via Insertion and Thermally Aware Routing in 3D ICs
Integrated Circuits and Systems, 2009Co-Authors: Sachin S. SapatnekarAbstract:Thermal challenges in 3D chips motivate the need for on-chip thermal conduction networks to deliver the heat to the heat sink. The most prominent example is a passive network of thermal Vias, which serves the function of heat conduction without necessarily serving any electrical function. This chapter begins with an overview of techniques for thermal via insertion. Next, it addresses the problem of 3D routing, overcoming challenges as conventional 2D routing is stretched to a third dimension and as electrical routes must vie with thermal Vias for scarce on-chip routing resources, particularly Intertier Vias.
Emre Salman - One of the best experts on this subject based on the ideXlab platform.
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ISCAS - Power and Data Integrity in Monolithic 3D Integrated SIMON Core
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019Co-Authors: Ivan Miketic, Emre SalmanAbstract:Monolithic 3D ICs have vertical interconnects that are comparable in size to local Vias, thereby permitting extremely fine-grained vertical integration. SIMON, a lightweight block cipher, is designed and characterized at the Graphic Database System (GDS) level in two types of monolithic 3D design styles: transistor-level, where nMOS and pMOS transistors are split between tiers, and gate-level, where individual gates are partitioned among the tiers. The two 3D implementations as well as a 2D implementation are compared and characterized in terms of area and power. Furthermore, the effect of monolithic Intertier Vias (MIVs) on power and data integrity is analyzed for each custom 3D design. It is shown that power delivery for transistor-level monolithic 3D design is more challenging since all of the pMOS transistors (that are connected to the supply voltage) are located in the bottom tier where there are limited metal resources due to technology constraints.
Abdullah Guler - One of the best experts on this subject based on the ideXlab platform.
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Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage
IEEE Transactions on Very Large Scale Integration Systems, 2019Co-Authors: Abdullah GulerAbstract:FinFETs have replaced planar MOSFETs due to their superior performance, power efficiency, and scalability. However, even FinFETs are expected to reach their scaling limits due to physical limits, process variations, and short-channel effects. As an alternative to device scaling, 3-D integrated circuits (ICs) can increase the number of transistors in a chip in the same footprint area. Among 3-D technologies, monolithic 3-D integration promises the highest density, performance, and power efficiency owing to its high-density monolithic Intertier Vias. A transistor-level monolithic implementation enables an independent optimization of transistor layers. However, it requires a new 3-D cell library. In this paper, we propose two new 3-D monolithic FinFET-based 8T SRAM cells and compare them with previously reported 6T and 8T SRAM cells implemented in 2-D/3-D. Both the proposed cells use pFinFET access transistors for better area efficiency in 3-D and low leakage current. One of the proposed cells utilizes independent-gate pFinFETs as pull-up transistors whose back gates are tied to the supply voltage for better writeability. This cell has 28.1% and 43.8% smaller footprint area, 31.6% and 43.2% smaller leakage current, and 53.2% and 29.0% lower read time compared with conventional 2-D 6T SRAM and 2-D 8T SRAM cells, respectively.
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Hybrid Monolithic 3-D IC Floorplanner
IEEE Transactions on Very Large Scale Integration Systems, 2018Co-Authors: Abdullah GulerAbstract:With continued technology scaling, interconnects have become the bottleneck in further performance and power consumption improvements in modern microprocessors. 3-D integrated circuits (3-D ICs) provide a promising approach for alleviating this bottleneck and enabling higher performance while reducing the footprint area, wirelength, and overall power consumption. Among various 3-D IC solutions, monolithic 3-D ICs stand out as they can utilize the third dimension most efficiently owing to high-density monolithic Intertier Vias. Monolithic integration is possible at different levels of granularity: block level, gate level, and transistor level. A hybrid monolithic design has modules implemented in different monolithic styles to further optimize the design objectives such as area, wirelength, and power consumption. However, a lack of electronic design automation tools makes the hybrid monolithic 3-D IC design quite challenging. In this paper, we introduce the first hybrid monolithic 3-D IC floorplanner. We characterize the OpenSPARC T2 processor core using different monolithic implementations and compare their footprint area, wirelength, power consumption, and temperature. We show, via simulations, that under the same timing constraint, a hybrid monolithic design offers 48.1% reduction in the footprint area and 14.6% reduction in power consumption compared to those of the 2-D design at the cost of higher power density and slightly higher temperature.
Ivan Miketic - One of the best experts on this subject based on the ideXlab platform.
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ISCAS - Power and Data Integrity in Monolithic 3D Integrated SIMON Core
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019Co-Authors: Ivan Miketic, Emre SalmanAbstract:Monolithic 3D ICs have vertical interconnects that are comparable in size to local Vias, thereby permitting extremely fine-grained vertical integration. SIMON, a lightweight block cipher, is designed and characterized at the Graphic Database System (GDS) level in two types of monolithic 3D design styles: transistor-level, where nMOS and pMOS transistors are split between tiers, and gate-level, where individual gates are partitioned among the tiers. The two 3D implementations as well as a 2D implementation are compared and characterized in terms of area and power. Furthermore, the effect of monolithic Intertier Vias (MIVs) on power and data integrity is analyzed for each custom 3D design. It is shown that power delivery for transistor-level monolithic 3D design is more challenging since all of the pMOS transistors (that are connected to the supply voltage) are located in the bottom tier where there are limited metal resources due to technology constraints.
Neil Goldsman - One of the best experts on this subject based on the ideXlab platform.
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A 3D Design: Light-powered Oscillator
2020Co-Authors: Zeynep Dilli, Neil GoldsmanAbstract:Part of the work on developing a self-contained sensor/computing network (“smart dust systems”) involves gaining a better of understanding of the challenges inherent in creating self-powered sensor units. There are several approaches which can be taken to solve this problem. Two of the main possibilities dependon harvesting ambient power from the environment, either from of RF electromagnetic waves or light. The design to be described here makes use of the latter in a 3D framework. The Lincoln Laboratories at MIT (MIT-LL) have developed a fully-depleted silicon-on-insulator process. Recently, they have taken steps to adopt this process to 3D chip stacking, by means of dense Intertier Vias. In late 2004, MIT-LL put out a call for proposals for an open run in this experimental process. Submissions for circuits to be implemented in a three-tier architecture within this process were solicited. The Semiconductor Simulation Group at the University of Maryland submitted a proposal for the design and implementation of a self-powered local oscillator, which was accepted. We were assigned a square layout area, 250 micrometers on one side. The design has since been submitted, and MIT-LL has informed us that they plan to commence the mask production by May 1st. In the following sections, we will first provide an outline of the system, and highlight the challenges involved in the design, including details of the process features that are relevant. A detailed section on the design will be followed by some simulation results and discussion.
