The Experts below are selected from a list of 6012 Experts worldwide ranked by ideXlab platform
David Z Pan - One of the best experts on this subject based on the ideXlab platform.
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a3map architecture aware analytic mapping for networks on chip
ACM Transactions on Design Automation of Electronic Systems, 2012Co-Authors: Wooyoung Jang, David Z PanAbstract:In this article, we propose novel and global Architecture-Aware Analytic MAPping (A3MAP) algorithms applied to Networks-on-Chip (NoCs) not only with homogeneous Processing Elements (PEs) on a regular Mesh network as done by most previous application mapping algorithms but also with heterogeneous PEs on an Irregular Mesh or custom network. As the main contributions, we develop a simple yet efficient interconnection matrix that can easily model any core graph and network. Then, an application mapping problem is exactly formulated to Mixed Integer Quadratic Programming (MIQP). Since MIQP is NP-hard, we propose two effective heuristics, a successive relaxation algorithm achieving short runtime, called A3MAP-SR and a genetic algorithm achieving high mapping quality, called A3MAP-GA. We also propose a partition-based application mapping approach for large-scale NoCs, which provides better trade-off between performance and runtime. Experimental results show that A3MAP algorithms reduce total hop count, compared to the previous application mapping algorithms optimized for a regular Mesh network, called NMAP [Murali and Micheli 2004] and for an Irregular Mesh and custom network, called CMAP [Tornero et al. 2008]. Furthermore, A3MAP algorithms make packets travel shorter distance than CMAP, which is related to energy consumption.
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a3map architecture aware analytic mapping for networks on chip
Asia and South Pacific Design Automation Conference, 2010Co-Authors: Wooyoung Jang, David Z PanAbstract:In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) not only with homogeneous cores on regular Mesh architecture as done by most previous mapping algorithms but also with heterogeneous cores on Irregular Mesh or custom architecture. As a main contribution, we develop a simple yet efficient interconnection matrix that models any task graph and network. Then, task mapping problem is exactly formulated to an MIQP (Mixed Integer Quadratic Programming). Since MIQP is NP-hard [15], we propose two effective heuristics, a successive relaxation algorithm and a genetic algorithm. Experimental results show that A3MAP by the successive relaxation algorithm reduces an amount of traffic up to 5.7%, 16.1% and 7.3% on average in regular Mesh, Irregular Mesh and custom network, respectively, compared to the previous state-of-the-art work [1]. A3MAP by the genetic algorithm reduces more traffic up to 8.8%, 29.4% and 16.1 % on average than [1] in regular Mesh, Irregular Mesh and custom network, respectively even if its runtime is longer.
Shuyen Lin - One of the best experts on this subject based on the ideXlab platform.
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topology aware adaptive routing for nonstationary Irregular Mesh in throttled 3d noc systems
IEEE Transactions on Parallel and Distributed Systems, 2013Co-Authors: Kunchih Chen, Shuyen Lin, Huishun HungAbstract:Three-dimensional network-on-chip (3D NoC) has been proposed to solve the complex on-chip communication issues in future 3D multicore systems. However, the thermal problems of 3D NoC are more serious than 2D NoC due to chip stacking. To keep the temperature below a certain thermal limit, the thermal emergent routers are usually throttled. Then, the topology of 3D NoC becomes a Nonstationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, some routing algorithms had been proposed in the previous works. However, the network still suffers from extremely traffic imbalance among lateral and vertical logic layer. In this paper, we propose a Topology Aware Adaptive Routing (TAAR) to balance the traffic load for NSI-Mesh in 3D NoC. TAAR has three routing modes, which can be dynamically adjusted based on the topology status of the routing path. In addition to increasing routing flexibility, the TAAR also increases both vertical and lateral path diversity to balance the traffic load. Compared with the related adaptive routing methods, the experimental results show that the proposed TAAR can reduce 19 to 295 percent traffic loads in the bottom logic layer and improve around 7.7 to 380 percent network throughput. According to our proposed VLSI architecture, the TAAR only needs less than 24.8 percent hardware overhead compared with the previous works.
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transport layer assisted routing for runtime thermal management of 3d noc systems
ACM Transactions in Embedded Computing Systems, 2013Co-Authors: Chihhao Chao, Kunchih Chen, Tsuchu Yin, Shuyen Lin, Anyeu WuAbstract:To ensure thermal safety and to avoid performance degradation from temperature regulation in 3D NoC, we propose a new temperature-traffic control framework. The framework contains the vertical throttling-based runtime thermal management (VT-RTM) scheme and the transport-layer assisted routing (TLAR) scheme. VT-RTM scheme increases the cooling speed and maintains high availability. TLAR scheme sustains the throughput of the nonstationary Irregular Mesh network. In our experiments, VT-RTM scheme reduces cooling time by 84p and achieves 98p network availability; the overall performance impact is around 8p of traditional schemes. TLAR scheme reduces average latency by 35∼p and improves sustainable throughput by 76p
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traffic balanced topology aware multiple routing adjustment for throttled 3d noc systems
Signal Processing Systems, 2012Co-Authors: Kunchih Chen, Shuyen Lin, Huishun HungAbstract:The thermal issue is important for 3D Network-on-Chip systems. To ensure the thermal safety, the near-overheat routers are throttled and the 3D topology becomes Non-Stationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, Transport Layer Assisted Routing (TLAR) scheme was proposed. It has better performance than the conventional routing approaches for NSI-Mesh. However, it still suffers significant traffic congestion in the bottom chip layer due to the insufficient lateral path diversities. To achieve more balanced traffic, we propose a Traffic-balanced Topology-aware Multiple Routing Adjustment (TTMRA). The experimental results show that the proposed TTMRA can improve 81.8% ~ 102.3% network throughput than TLAR scheme.
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transport layer assisted routing for non stationary Irregular Mesh of thermal aware 3d network on chip systems
Symposium on Cloud Computing, 2011Co-Authors: Chihhao Chao, Tsuchu Yin, Shuyen LinAbstract:Thermal issue is important for 3D Network-on-Chip systems. To ensure thermal safety, run-time thermal management is required. However, the regulation of temperature requires throttling of the near-overheated router, which makes the topology become Non-Stationary Irregular Mesh (NSI-Mesh). To successfully deliver packet in NSI-Mesh, we propose the Transport Layer Assisted Routing (TLAR) scheme and two algorithms for thermal-aware 3D NoC. Based on the experimental results, the proposed routing scheme can reduce the latency over 57.5% and improve the throughput above 1.47x.
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traffic balanced routing algorithm for Irregular Mesh based on chip networks
IEEE Transactions on Computers, 2008Co-Authors: Shuyen Lin, Chihhao Chao, Chunhsiang Huang, Kenghsien HuangAbstract:On-chip networks (OCNs) have been proposed to solve the increasing scale and complexity of the designs in nanoscale multicore VLSI designs. The concept of Irregular Meshes is an important issue because IPs of different sizes may be supported by various vendors. In order to solve routing problems in Irregular Meshes, modified routing algorithms to detour oversized IPs (OIPs) are needed. However, directly applying fault-tolerant routing algorithms may cause two serious problems: 1) heavy traffic loads around OIPs and 2) unbalanced traffic loads in Irregular Meshes. In this paper, we propose an OIP avoidance prerouting (OAPR) algorithm to solve the aforementioned problems. The proposed OAPR can make traffic loads evenly spread on the networks and shorten the average paths of packets. Therefore, the networks using the OAPR have lower latency and higher throughput than those using fault- tolerant routing algorithms. In our experiments, four different cases are simulated to demonstrate that the proposed OAPR improves 13.3 percent to 100 percent sustainable throughputs than two previous fault-tolerant routing algorithms. Moreover, the hardware overhead of the OAPR is less than 1 percent compared to the cost of a whole router. Hence, the proposed OAPR algorithm has good performance and is practical for Irregular Mesh-based OCNs.
Wooyoung Jang - One of the best experts on this subject based on the ideXlab platform.
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a3map architecture aware analytic mapping for networks on chip
ACM Transactions on Design Automation of Electronic Systems, 2012Co-Authors: Wooyoung Jang, David Z PanAbstract:In this article, we propose novel and global Architecture-Aware Analytic MAPping (A3MAP) algorithms applied to Networks-on-Chip (NoCs) not only with homogeneous Processing Elements (PEs) on a regular Mesh network as done by most previous application mapping algorithms but also with heterogeneous PEs on an Irregular Mesh or custom network. As the main contributions, we develop a simple yet efficient interconnection matrix that can easily model any core graph and network. Then, an application mapping problem is exactly formulated to Mixed Integer Quadratic Programming (MIQP). Since MIQP is NP-hard, we propose two effective heuristics, a successive relaxation algorithm achieving short runtime, called A3MAP-SR and a genetic algorithm achieving high mapping quality, called A3MAP-GA. We also propose a partition-based application mapping approach for large-scale NoCs, which provides better trade-off between performance and runtime. Experimental results show that A3MAP algorithms reduce total hop count, compared to the previous application mapping algorithms optimized for a regular Mesh network, called NMAP [Murali and Micheli 2004] and for an Irregular Mesh and custom network, called CMAP [Tornero et al. 2008]. Furthermore, A3MAP algorithms make packets travel shorter distance than CMAP, which is related to energy consumption.
-
a3map architecture aware analytic mapping for networks on chip
Asia and South Pacific Design Automation Conference, 2010Co-Authors: Wooyoung Jang, David Z PanAbstract:In this paper, we propose a novel and global A3MAP (Architecture-Aware Analytic Mapping) algorithm applied to NoC (Networks-on-Chip) based MPSoC (Multi-Processor System-on-Chip) not only with homogeneous cores on regular Mesh architecture as done by most previous mapping algorithms but also with heterogeneous cores on Irregular Mesh or custom architecture. As a main contribution, we develop a simple yet efficient interconnection matrix that models any task graph and network. Then, task mapping problem is exactly formulated to an MIQP (Mixed Integer Quadratic Programming). Since MIQP is NP-hard [15], we propose two effective heuristics, a successive relaxation algorithm and a genetic algorithm. Experimental results show that A3MAP by the successive relaxation algorithm reduces an amount of traffic up to 5.7%, 16.1% and 7.3% on average in regular Mesh, Irregular Mesh and custom network, respectively, compared to the previous state-of-the-art work [1]. A3MAP by the genetic algorithm reduces more traffic up to 8.8%, 29.4% and 16.1 % on average than [1] in regular Mesh, Irregular Mesh and custom network, respectively even if its runtime is longer.
Kunchih Chen - One of the best experts on this subject based on the ideXlab platform.
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thermal aware dynamic buffer allocation for proactive routing algorithm on 3d network on chip systems
International Symposium on VLSI Design Automation and Test, 2014Co-Authors: Yuansheng Lee, Kunchih Chen, Hsienkai Hsin, Enjui ChangAbstract:The thermal problems of three-dimensional Network-on-Chip (3D NoC) systems become more serious because of die stacking and different thermal conductance between layers. Up to now, most previous works cannot further achieve thermal balance of the 3D NoC systems since they consider either only temperature or only traffic information. We propose a Proactive Thermal-Dynamic-Buffer Allocation (PTDBA) scheme to constrain the routing resource around overheated regions. In addition, we reduce the frequency of packets switching in overheated router regions. By doing so, we can slow down the rate of temperature increment. Based on the proposed PTDBA, we can redistribute traffic load by means of buffer occupancy. The experimental results show that the proposed scheme can reduce the deviation of temperature distribution by 25.6% and help to improve network throughput in non-stationary Irregular Mesh by 74.8% compared with PTB3R.
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topology aware adaptive routing for nonstationary Irregular Mesh in throttled 3d noc systems
IEEE Transactions on Parallel and Distributed Systems, 2013Co-Authors: Kunchih Chen, Shuyen Lin, Huishun HungAbstract:Three-dimensional network-on-chip (3D NoC) has been proposed to solve the complex on-chip communication issues in future 3D multicore systems. However, the thermal problems of 3D NoC are more serious than 2D NoC due to chip stacking. To keep the temperature below a certain thermal limit, the thermal emergent routers are usually throttled. Then, the topology of 3D NoC becomes a Nonstationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, some routing algorithms had been proposed in the previous works. However, the network still suffers from extremely traffic imbalance among lateral and vertical logic layer. In this paper, we propose a Topology Aware Adaptive Routing (TAAR) to balance the traffic load for NSI-Mesh in 3D NoC. TAAR has three routing modes, which can be dynamically adjusted based on the topology status of the routing path. In addition to increasing routing flexibility, the TAAR also increases both vertical and lateral path diversity to balance the traffic load. Compared with the related adaptive routing methods, the experimental results show that the proposed TAAR can reduce 19 to 295 percent traffic loads in the bottom logic layer and improve around 7.7 to 380 percent network throughput. According to our proposed VLSI architecture, the TAAR only needs less than 24.8 percent hardware overhead compared with the previous works.
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transport layer assisted routing for runtime thermal management of 3d noc systems
ACM Transactions in Embedded Computing Systems, 2013Co-Authors: Chihhao Chao, Kunchih Chen, Tsuchu Yin, Shuyen Lin, Anyeu WuAbstract:To ensure thermal safety and to avoid performance degradation from temperature regulation in 3D NoC, we propose a new temperature-traffic control framework. The framework contains the vertical throttling-based runtime thermal management (VT-RTM) scheme and the transport-layer assisted routing (TLAR) scheme. VT-RTM scheme increases the cooling speed and maintains high availability. TLAR scheme sustains the throughput of the nonstationary Irregular Mesh network. In our experiments, VT-RTM scheme reduces cooling time by 84p and achieves 98p network availability; the overall performance impact is around 8p of traditional schemes. TLAR scheme reduces average latency by 35∼p and improves sustainable throughput by 76p
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traffic balanced topology aware multiple routing adjustment for throttled 3d noc systems
Signal Processing Systems, 2012Co-Authors: Kunchih Chen, Shuyen Lin, Huishun HungAbstract:The thermal issue is important for 3D Network-on-Chip systems. To ensure the thermal safety, the near-overheat routers are throttled and the 3D topology becomes Non-Stationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, Transport Layer Assisted Routing (TLAR) scheme was proposed. It has better performance than the conventional routing approaches for NSI-Mesh. However, it still suffers significant traffic congestion in the bottom chip layer due to the insufficient lateral path diversities. To achieve more balanced traffic, we propose a Traffic-balanced Topology-aware Multiple Routing Adjustment (TTMRA). The experimental results show that the proposed TTMRA can improve 81.8% ~ 102.3% network throughput than TLAR scheme.
Huishun Hung - One of the best experts on this subject based on the ideXlab platform.
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topology aware adaptive routing for nonstationary Irregular Mesh in throttled 3d noc systems
IEEE Transactions on Parallel and Distributed Systems, 2013Co-Authors: Kunchih Chen, Shuyen Lin, Huishun HungAbstract:Three-dimensional network-on-chip (3D NoC) has been proposed to solve the complex on-chip communication issues in future 3D multicore systems. However, the thermal problems of 3D NoC are more serious than 2D NoC due to chip stacking. To keep the temperature below a certain thermal limit, the thermal emergent routers are usually throttled. Then, the topology of 3D NoC becomes a Nonstationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, some routing algorithms had been proposed in the previous works. However, the network still suffers from extremely traffic imbalance among lateral and vertical logic layer. In this paper, we propose a Topology Aware Adaptive Routing (TAAR) to balance the traffic load for NSI-Mesh in 3D NoC. TAAR has three routing modes, which can be dynamically adjusted based on the topology status of the routing path. In addition to increasing routing flexibility, the TAAR also increases both vertical and lateral path diversity to balance the traffic load. Compared with the related adaptive routing methods, the experimental results show that the proposed TAAR can reduce 19 to 295 percent traffic loads in the bottom logic layer and improve around 7.7 to 380 percent network throughput. According to our proposed VLSI architecture, the TAAR only needs less than 24.8 percent hardware overhead compared with the previous works.
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traffic balanced topology aware multiple routing adjustment for throttled 3d noc systems
Signal Processing Systems, 2012Co-Authors: Kunchih Chen, Shuyen Lin, Huishun HungAbstract:The thermal issue is important for 3D Network-on-Chip systems. To ensure the thermal safety, the near-overheat routers are throttled and the 3D topology becomes Non-Stationary Irregular Mesh (NSI-Mesh). To ensure the successful packet delivery in the NSI-Mesh, Transport Layer Assisted Routing (TLAR) scheme was proposed. It has better performance than the conventional routing approaches for NSI-Mesh. However, it still suffers significant traffic congestion in the bottom chip layer due to the insufficient lateral path diversities. To achieve more balanced traffic, we propose a Traffic-balanced Topology-aware Multiple Routing Adjustment (TTMRA). The experimental results show that the proposed TTMRA can improve 81.8% ~ 102.3% network throughput than TLAR scheme.
