The Experts below are selected from a list of 2484 Experts worldwide ranked by ideXlab platform
Takashi Hikihara - One of the best experts on this subject based on the ideXlab platform.
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hf gate drive circuit for a normally on sic JFET with inherent safety
European Conference on Power Electronics and Applications, 2009Co-Authors: Tsuguhiro Takuno, Takashi Hikihara, Takashi Tsuno, Satoshi HatsukawaAbstract:A gate drive circuit for a silicon carbide (SiC) JFET is introduced from the standpoint of application to power conversion circuit. This gate drive circuit enables normally-on JFETs as close as normally-off devices at high switching frequency. The voltage and current responses of the implemented circuit are discussed under loads at the switching frequencies over 1MHz.
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Power conversion with SiC devices at extremely high ambient temperatures
IEEE Transactions on Power Electronics, 2007Co-Authors: Tatsuya Funaki, J Junghans, A S Kashyap, Fred Barlow, Homer Alan Mantooth, Juan Carlos Balda, Tsunenobu Kimoto, Takashi HikiharaAbstract:This paper evaluates the capability of SiC power semiconductor devices, in particular JFET and Schottky barrier diodes (SBD) for application in high-temperature power electronics. SiC JFETs and SBDs were packaged in high temperature packages to measure the dc characteristics of these SiC devices at ambient temperatures ranging from 25degC (room temperature) up to 450degC. The results show that both devices can operate at 450degC, which is impossible for conventional Si devices, at the expense of significant derating. The current capability of the SiC SBD does not change with temperature, but as expected the JFET current decreases with rising temperatures. A 100 V, 25 W dc-dc converter is used as an example of a high-temperature power-electronics circuit because of circuit simplicity. The converter is designed and built in accordance with the static characteristics of the SiC devices measured under extremely high ambient temperatures, and then tested up to an ambient temperature of 400degC. The conduction loss of the SiC JFET increases slightly with increasing temperatures, as predicted from its dc characteristics, but its switching characteristics hardly change. Thus, SiC devices are well suited for operation in harsh temperature environments like aerospace and automotive applications.
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characterization of sic JFET for temperature dependent device modeling
Power Electronics Specialists Conference, 2006Co-Authors: Tsuyoshi Funaki, Homer Alan Mantooth, Juan Carlos Balda, Avinash Srikrishnan Kashyap, F Barlow, Tatsuya Kimoto, Takashi HikiharaAbstract:Silicon Carbide (SiC) is considered the wide band gap semiconductor material that can presently compete with silicon (Si) material for power switching devices. Compact circuit simulation models for SiC devices are of utmost importance for designing and analyzing converter circuits; in particular, if comparisons with Si devices will be performed. The SiC power switching device structure and composition inevitably differs from those of conventional Si devices so as to harness the superiority of the material. The operational characteristics of the device thus are different from those of conventional Si devices. These characteristics cannot be accurately predicted by current Si power device models. Hence, the motivation to develop circuit simulation models for SiC devices. Moreover, SiC transistors have not been characterized as thoroughly as diodes. This paper characterizes SiC JFETs for the purpose of modeling and parameter extraction which can then be utilized in circuit simulations. The characterization is based on the dc (current-voltage) characteristic measurements using a curve tracer and on the ac (capacitance [impedance] — voltage) measurements using an impedance analyzer. Noting that characterization data for SiC JFETs are only available up to an ambient temperature of 250°C, the device is characterized from room temperature to 450°C demonstrating the high temperature operation of SiC JFETs. To this end, the devices were packaged in dedicated high temperature packages, and measurement fixtures were specially fabricated to withstand high ambient temperatures. The body diode buried in the evaluated SiC JFET is also characterized for potential synchronous rectifier applications.
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switching characteristics of sic JFET and schottky diode in high temperature dc dc power converters
IEICE Electronics Express, 2005Co-Authors: Tsuyoshi Funaki, J Junghans, Juan Carlos Balda, Tsunenobu Kimoto, F Barlow, Anuwat Jangwanitlert, Sharmila Mounce, Alan H Mantooth, Takashi HikiharaAbstract:This paper reports on SiC devices operating in a dc-dc buck converter under extremely high ambient temperatures. To this end, the authors packaged SiC JFET and Schottky diodes in thermally stable packages and built a high-temperature inductor. The converter was tested at ambient temperatures up to 400°C. Although the conduction loss of the SiC JFET increases slightly with increasing temperatures, the SiC JFET and Schottky diode continue normal operation because their switching characteristics show minimal change with temperature. This work further demonstrates the suitability of the SiC devices for high-temperature power converter applications.
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sic JFET dc characteristics under extremely high ambient temperatures
IEICE Electronics Express, 2004Co-Authors: Tsuyoshi Funaki, J Junghans, Juan Carlos Balda, Tsunenobu Kimoto, Avinash Srikrishnan Kashyap, F Barlow, Alan H Mantooth, Takashi HikiharaAbstract:This paper reports on the measured dc characteristics of a SiC JFET device from room temperature up to 450°C in order to evaluate the device's capability for high-temperature operation. The authors packaged SiC JFET bare die into a dedicated high-temperature package to be able to perform experiments under extremely high ambient temperatures. The experimental results show that the device can operate at 450°C, which is impossible for conventional Si devices, but the current capability of the SiC JFET diminishes with rising temperatures. For example, the saturation current becomes 20% at 450°C with respect to the value at the room temperature.
Matthias Bucher - One of the best experts on this subject based on the ideXlab platform.
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compact modeling of low frequency noise and thermal noise in junction field effect transistors
European Solid-State Device Research Conference, 2019Co-Authors: Nikolaos Makris, Loukas Chevas, Matthias BucherAbstract:This paper presents a novel charge-based approach to modeling bias-dependent noise in junction field-effect transistors (JFETs). Low frequency noise as well as thermal noise aspects are modeled within the recent charge-based model of the double-gate (DG) JFET. For low frequency noise, mobility fluctuations according to the Hooge model is addressed. Thermal noise is expressed within the charge-based modeling approach. The models are validated with respect to TCAD simulations and show correct dependence over a range of gate and drain bias. A custom setup for low frequency noise measurement of JFETs is described. Noise measurements of n-JFETs are discussed, and the compact model is compared with the measurement.
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charge based modeling of long channel symmetric double gate junction fets part i drain current and transconductances
IEEE Transactions on Electron Devices, 2018Co-Authors: Nikolaos Makris, Jeanmichel Sallese, Farzan Jazaeri, Rupendra Kumar Sharma, Matthias BucherAbstract:The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET.
Bucher Matthias(http://users.isc.tuc.gr/~mbucher) - One of the best experts on this subject based on the ideXlab platform.
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Compact modeling of low frequency noise and thermal noise in junction field effect transistors
Institute of Electrical and Electronics Engineers, 2019Co-Authors: Μακρης Νικολαος(http://users.isc.tuc.gr/~nmakris), Makris Nikolaos(http://users.isc.tuc.gr/~nmakris), Χεβας Λουκας(http://users.isc.tuc.gr/~lchevas), Chevas Loukas(http://users.isc.tuc.gr/~lchevas), Bucher Matthias(http://users.isc.tuc.gr/~mbucher)Abstract:Summarization: This paper presents a novel charge-based approach to modeling bias-dependent noise in junction field-effect transistors (JFETs). Low frequency noise as well as thermal noise aspects are modeled within the recent charge-based model of the double-gate (DG) JFET. For low frequency noise, mobility fluctuations according to the Hooge model is addressed. Thermal noise is expressed within the charge-based modeling approach. The models are validated with respect to TCAD simulations and show correct dependence over a range of gate and drain bias. A custom setup for low frequency noise measurement of JFETs is described. Noise measurements of n-JFETs are discussed, and the compact model is compared with the measurement.Presented on
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CJM: a compact model for double-gate junction FETs
'Institute of Electrical and Electronics Engineers (IEEE)', 2019Co-Authors: Μακρης Νικολαος(http://users.isc.tuc.gr/~nmakris), Makris Nikolaos(http://users.isc.tuc.gr/~nmakris), Bucher Matthias(http://users.isc.tuc.gr/~mbucher), Jazaeri, Farzan 1984-(http://viaf.org/viaf/68145304358278570306), Sallese, Jean-michel 1964-(http://viaf.org/viaf/1057145857143022922975)Abstract:Summarization: The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of device fabrication but also its principle of operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Furthermore, co-integration of JFET with CMOS technology is attractive. Physics-based compact models for JFETs are however scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, transconductances and transcapacitances of symmetric DG JFETs, covering all regions of device operation, continuously from subthreshold to linear and saturation operation. This charge-based JFET model (called CJM) constitutes the basis of a full compact model of the DG JFET for analog, RF, and digital circuit simulation.Παρουσιάστηκε στο: IEEE Journal of the Electron Devices Societ
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Charge-based modeling of long-channel symmetric double-gate junction FETs-Part I: drain current and transconductances
Institute of Electrical and Electronics Engineers, 2018Co-Authors: Μακρης Νικολαος(http://users.isc.tuc.gr/~nmakris), Makris Nikolaos(http://users.isc.tuc.gr/~nmakris), Bucher Matthias(http://users.isc.tuc.gr/~mbucher), Jazaeri, Farzan 1984-(http://viaf.org/viaf/68145304358278570306), Sallese, Jean-michel 1964-(http://viaf.org/viaf/1057145857143022922975), Sharma Rupendra Kumar()Abstract:Summarization: The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET.Presented on: IEEE Transactions on Electron Device
Nikolaos Makris - One of the best experts on this subject based on the ideXlab platform.
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compact modeling of low frequency noise and thermal noise in junction field effect transistors
European Solid-State Device Research Conference, 2019Co-Authors: Nikolaos Makris, Loukas Chevas, Matthias BucherAbstract:This paper presents a novel charge-based approach to modeling bias-dependent noise in junction field-effect transistors (JFETs). Low frequency noise as well as thermal noise aspects are modeled within the recent charge-based model of the double-gate (DG) JFET. For low frequency noise, mobility fluctuations according to the Hooge model is addressed. Thermal noise is expressed within the charge-based modeling approach. The models are validated with respect to TCAD simulations and show correct dependence over a range of gate and drain bias. A custom setup for low frequency noise measurement of JFETs is described. Noise measurements of n-JFETs are discussed, and the compact model is compared with the measurement.
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charge based modeling of long channel symmetric double gate junction fets part i drain current and transconductances
IEEE Transactions on Electron Devices, 2018Co-Authors: Nikolaos Makris, Jeanmichel Sallese, Farzan Jazaeri, Rupendra Kumar Sharma, Matthias BucherAbstract:The double-gate (DG) junction field-effect transistor (JFET) is a classical electron device, with a simple structure that presents many advantages in terms of not only device fabrication but also its operation. The device has been largely used in low-noise applications, but also more recently, in power electronics. Physics-based compact models for JFETs, contrary to MOSFETs, are, however, scarce. In this paper, an analytical, charge-based model is established for the mobile charges, drain current, and transconductances of symmetric DG JFETs, covering all regions of device operation. The model is unified and continuous from subthreshold to linear and saturation operation and is valid over a large temperature range. This charge-based model constitutes the basis of a full compact model of the DG JFET.
J.c. Zolper - One of the best experts on this subject based on the ideXlab platform.
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epitaxially grown gan junction field effect transistors
IEEE Transactions on Electron Devices, 2000Co-Authors: L Zhang, R J Shul, A G Baca, L F Lester, P C Chang, C G Willison, U K Mishra, Steven P Denbaars, J.c. ZolperAbstract:Junction field effect transistors (JFETs) are fabricated on a GaN epitaxial structure grown by metal organic chemical vapor deposition (MOCVD). The dc and microwave characteristics of the device are presented. A junction breakdown voltage of 56 V is obtained corresponding to the theoretical limit of the breakdown field in GaN for the doping levels used. A maximum extrinsic transconductance (g/sub m/) of 48 mS/mm and a maximum source-drain current of 270 mA/mm are achieved on a 0.8 /spl mu/m gate JFET device at V/sub GS/=1 V and V/sub DS/=15 V. The intrinsic transconductance, calculated from the measured g/sub m/ and the source series resistance, is 81 mS/mm. The f/sub T/ and f/sub max/ for these devices are 6 GHz and 12 GHz, respectively. These JFET's exhibit a significant current reduction after a high drain bias is applied, which is attributed to a partially depleted channel caused by trapped hot-electrons in the semi-insulating GaN buffer layer. A theoretical model describing the current collapse is presented, and an estimate for the length of the trapped electron region is given.
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A review of junction field effect transistors for high-temperature and high-power electronics
Solid-State Electronics, 1998Co-Authors: J.c. ZolperAbstract:Abstract The status of GaAs, SiC and GaN junction field effect transistors (JFETs) is reviewed with a focus on their application to high temperature and high power operation. The advantage of the JFET structure for this operation regime is detailed. Future directions for junction gated transistors are outlined.
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ion implanted gan junction field effect transistor
Applied Physics Letters, 1996Co-Authors: J.c. Zolper, R J Shul, A G Baca, R G Wilson, S J Pearton, Richard A StallAbstract:Selective area ion implantation doping has been used to fabricate GaN junction field effect transistors (JFETs). p‐type and n‐type doping was achieved with Ca and Si implantation, respectively, followed by a 1150 °C rapid thermal anneal. A refractory W gate contact was employed that allows the p‐gate region to be self‐aligned to the gate contact. A gate turn‐on voltage of 1.84 V at 1 mA/mm of gate current was achieved. For a ∼1.7 μm×50 μm JFET with a −6 V threshold voltage, a maximum transconductance of 7 mS/mm at VGS=− 2V and saturation current of 33 mA/mm at VGS=0 V were measured. These results were limited by excess access resistance and can be expected to be improved with optimized n+ implants in the source and drain regions.