L1 Cache

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The Experts below are selected from a list of 20268 Experts worldwide ranked by ideXlab platform

A. Farhang - One of the best experts on this subject based on the ideXlab platform.

Muhammad M. Khellah - One of the best experts on this subject based on the ideXlab platform.

Dinesh Somasekhar - One of the best experts on this subject based on the ideXlab platform.

Tianzhou Chen - One of the best experts on this subject based on the ideXlab platform.

  • an energy efficient scheme for stt ram L1 Cache
    High Performance Computing and Communications, 2013
    Co-Authors: Jun Yao, Tianzhou Chen
    Abstract:

    Spin-Transfer Torque RAM (STT-RAM) is a promising Cache candidate studied frequently in recent years. Compared to the traditional SRAM, The STT-RAM is more promising for future on-chip Caches due to STT-RAM's long endurance, low leakage, high density and high access speed. Nevertheless, the major challenges of using STT-RAM as L1 Cache are its write energy and write latency. It is feasible to use STT-RAM as L1 Cache by reducing data retention time. We find that most data in L1 Cache has a life time shorter than STT-RAM data retention time. A refresh scheme that will degrades system performance, and bring more energy consumption is needed to assure data correctness. In this paper, we proposed a counter-controlled scheme to avoid STT-RAM L1 Cache data block refreshing. We propose a dead data processing strategy that deals with data block when it exceeds its retention time. Our simulation results show that STT-RAM L1 Cache coupled with our counter-controlled scheme can save up to 60% energy consumption, 44% energy consumption on average compared to SRAM L1 Cache, achieve slightly performance improvement on average compared to baseline.

  • L1 collective Cache managing shared data for chip multiprocessors
    Lecture Notes in Computer Science, 2009
    Co-Authors: Guanjun Jiang, Degui Fen, Liangliang Tong, Lingxiang Xiang, Chao Wang, Tianzhou Chen
    Abstract:

    In recent years, with the possible end of further improvements in single processor, more and more researchers shift to the idea of Chip Multiprocessors (CMPs). The burgeoning of multi-thread programs brings on dramatically increased inter-core communication. Unfortunately, traditional architectures fail to meet the challenge, as they conduct such a kind of communication on the last level of on-chip Cache or even on the memory.This paper proposes a novel approach, called Collective Cache, to differentiate the access to shared/private data and handle data communication on the first level Cache. In the proposed Cache architecture, the share data found in the last level Cache are moved into the Collective Cache, a L1 Cache structure shared by all cores. We show that the mechanism this paper proposed can immensely enhance inter-processors communication, increase the usage efficiency of L1 Cache and simplify data consistency protocol. Extensive analysis of this approach with Simics shows that it can reduce the L1 Cache miss rate by 3.36%.

Zhenyu Sun - One of the best experts on this subject based on the ideXlab platform.

  • a coherent hybrid sram and stt ram L1 Cache architecture for shared memory multicores
    Asia and South Pacific Design Automation Conference, 2014
    Co-Authors: Jianxing Wang, Yenni Tim, Wengfai Wong, Zhongliang Ong, Zhenyu Sun
    Abstract:

    STT-RAM is an emerging NVRAM technology that promises high density, low energy and a comparable access speed to conventional SRAM. This paper proposes a hybrid L1 Cache architecture that incorporates both SRAM and STT-RAM. The key novelty of the proposal is the exploition of the MESI Cache coherence protocol to perform dynamic block reallocation between different Cache partitions. Compared to the pure SRAM-based design, our hybrid scheme achieves 38% of energy saving with a mere 0.8% IPC degradation while extending the lifespan of STT-RAM partition at the same time.