The Experts below are selected from a list of 12366 Experts worldwide ranked by ideXlab platform
Rishikesh Pandey - One of the best experts on this subject based on the ideXlab platform.
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a very Low Output Resistance and wide swing class ab level shifted folded flipped voltage folLower cell
Integration, 2021Co-Authors: Caffey Jindal, Rishikesh PandeyAbstract:Abstract The paper presents a class-AB flipped voltage folLower (FVF) cell. In contrast to previous works in the literature, FVF cell, level shifter and folded FVF cell are merged in the proposed FVF cell to offer class-AB operation along with wide input/Output voltage swing and Low Output Resistance. In the proposed FVF cell, the level shifter increases the input/Output voltage swing while the folding transistor provides an alternate path for sourcing current, which results in Low Output Resistance. The proposed FVF cell offers wide input/Output voltage swing of 0.80 V/0.67 V, high gain of 0.84, wide bandwidth of 54 MHz for the worst case load capacitance of 50 pF and Low Output Resistance of 10 Ω. The proposed FVF cell is simulated using Cadence Virtuoso Analog Design Environment in 180 nm CMOS technology. The physical layout has been designed using Cadence Virtuoso Layout XL editor and post-layout simulation results are presented to demonstrate the performance of the proposed FVF cell. The corner analysis has also been performed to show the robustness of the proposed FVF cell.
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high slew rate and very Low Output Resistance class ab flipped voltage folLower cell for Low voltage Low power analog circuits
Wireless Personal Communications, 2021Co-Authors: Caffey Jindal, Rishikesh PandeyAbstract:A Low Output Resistance and high slew rate class-AB flipped voltage folLower (FVF) cell is presented in this paper. The proposed FVF cell consists of cascoding transistor which provides the extra gain to the feedback loop and leads to the Low Output Resistance while the bulk-driven transistor acts as an adjustable current source to increase the current driving capability and slew rate. The proposed FVF cell offers numerous advantages such as Low Output Resistance, high current driving capability, wide bandwidth, high symmetrical slew rate and occupies less chip area. The proposed circuit has been designed using Cadence virtuoso tool in 0.18 µm CMOS technology and the post-layout simulation results are presented to validate its performance. To show the performance under extreme conditions, the analysis of the proposed circuit at various corners has also been presented.
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Class-AB Flipped Voltage FolLower Cell with High Current Driving Capability and Low Output Resistance for High Frequency Applications
Wireless Personal Communications, 2021Co-Authors: Caffey Jindal, Rishikesh PandeyAbstract:In this paper, a class-AB flipped voltage folLower cell with high current driving capability is proposed. The proposed flipped voltage folLower (FVF) cell offers increased current sourcing capability and large input/Output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between Output and ground terminals to increase the current sinking capability and to reduce the Output Resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit.
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high slew rate and Low Output Resistance class ab flipped voltage folLower cell with increased current driving capability
Sadhana-academy Proceedings in Engineering Sciences, 2020Co-Authors: Caffey Jindal, Rishikesh PandeyAbstract:The paper proposes a class-AB flipped voltage folLower (FVF) cell, in which the bulk-driven transistor is used as an input transistor with a replica-biased scheme to eliminate the DC level shift while a cascoding transistor is used to reduce the Output Resistance. The proposed FVF cell has several advantages such as Low Output Resistance, approximately unity voltage gain, high symmetrical slew rate, high current sourcing capability, high current sinking capability and wide bandwidth. The proposed FVF cell has been simulated in Cadence Virtuoso Analog Design Environment using BSIM3v3 180 nm CMOS technology with a power supply voltage of 1.2 V.
Caffey Jindal - One of the best experts on this subject based on the ideXlab platform.
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a very Low Output Resistance and wide swing class ab level shifted folded flipped voltage folLower cell
Integration, 2021Co-Authors: Caffey Jindal, Rishikesh PandeyAbstract:Abstract The paper presents a class-AB flipped voltage folLower (FVF) cell. In contrast to previous works in the literature, FVF cell, level shifter and folded FVF cell are merged in the proposed FVF cell to offer class-AB operation along with wide input/Output voltage swing and Low Output Resistance. In the proposed FVF cell, the level shifter increases the input/Output voltage swing while the folding transistor provides an alternate path for sourcing current, which results in Low Output Resistance. The proposed FVF cell offers wide input/Output voltage swing of 0.80 V/0.67 V, high gain of 0.84, wide bandwidth of 54 MHz for the worst case load capacitance of 50 pF and Low Output Resistance of 10 Ω. The proposed FVF cell is simulated using Cadence Virtuoso Analog Design Environment in 180 nm CMOS technology. The physical layout has been designed using Cadence Virtuoso Layout XL editor and post-layout simulation results are presented to demonstrate the performance of the proposed FVF cell. The corner analysis has also been performed to show the robustness of the proposed FVF cell.
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high slew rate and very Low Output Resistance class ab flipped voltage folLower cell for Low voltage Low power analog circuits
Wireless Personal Communications, 2021Co-Authors: Caffey Jindal, Rishikesh PandeyAbstract:A Low Output Resistance and high slew rate class-AB flipped voltage folLower (FVF) cell is presented in this paper. The proposed FVF cell consists of cascoding transistor which provides the extra gain to the feedback loop and leads to the Low Output Resistance while the bulk-driven transistor acts as an adjustable current source to increase the current driving capability and slew rate. The proposed FVF cell offers numerous advantages such as Low Output Resistance, high current driving capability, wide bandwidth, high symmetrical slew rate and occupies less chip area. The proposed circuit has been designed using Cadence virtuoso tool in 0.18 µm CMOS technology and the post-layout simulation results are presented to validate its performance. To show the performance under extreme conditions, the analysis of the proposed circuit at various corners has also been presented.
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Class-AB Flipped Voltage FolLower Cell with High Current Driving Capability and Low Output Resistance for High Frequency Applications
Wireless Personal Communications, 2021Co-Authors: Caffey Jindal, Rishikesh PandeyAbstract:In this paper, a class-AB flipped voltage folLower cell with high current driving capability is proposed. The proposed flipped voltage folLower (FVF) cell offers increased current sourcing capability and large input/Output voltage swing due to the use of bulk-driven and level shifter techniques, respectively. Further, it uses an additional NMOS transistor connected between Output and ground terminals to increase the current sinking capability and to reduce the Output Resistance. The stability analysis has been performed by using Routh–Hurwitz stability criteria which confirms that the proposed FVF cell is stable. The proposed FVF cell also offers a high symmetrical slew rate. The proposed FVF cell has been simulated in Cadence virtuoso analog design environment using BSIM3v3 180 nm CMOS technology and simulation results are presented to validate the effectiveness of the proposed circuit.
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high slew rate and Low Output Resistance class ab flipped voltage folLower cell with increased current driving capability
Sadhana-academy Proceedings in Engineering Sciences, 2020Co-Authors: Caffey Jindal, Rishikesh PandeyAbstract:The paper proposes a class-AB flipped voltage folLower (FVF) cell, in which the bulk-driven transistor is used as an input transistor with a replica-biased scheme to eliminate the DC level shift while a cascoding transistor is used to reduce the Output Resistance. The proposed FVF cell has several advantages such as Low Output Resistance, approximately unity voltage gain, high symmetrical slew rate, high current sourcing capability, high current sinking capability and wide bandwidth. The proposed FVF cell has been simulated in Cadence Virtuoso Analog Design Environment using BSIM3v3 180 nm CMOS technology with a power supply voltage of 1.2 V.
Bouman L.s. - One of the best experts on this subject based on the ideXlab platform.
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An FM Chirp Waveform Generator and Detector for Radar: Baseband, intermediate frequency, Low noise and RF power amplifiers
2020Co-Authors: Sabti A., Bouman L.s.Abstract:This report describes the design of different amplifiers that are part of an FM transceiver. This is part of a larger project, which has the objective to design a complete FM transceiver from discrete components only, meaning that IC technology is not considered. The circuits designed are two baseband amplifiers, an intermediate frequency amplifier, a Low noise amplifier and an RF power amplifier. The baseband amplifiers are implemented with a Darlington pair in common-collector configuration to achieve a high input Resistance, Low Output Resistance, and unity gain transfer. The intermediate frequency amplifier is centered at 9.95 MHz with a -3dB bandwidth of 2 MHz. The maximum gain is 40.5 dB and can be Lowered with up to 39.7 dB using a potentiometer, based on the emitter degeneration principle. The Low noise amplifier has a maximum noise figure of 1.4 dB over the RF carrier band of 88 to 108 MHz. It has a gain of 33 dB, and reaches its 1 dB compression point for an input of -33 dBm. The total harmonic distortion is less than 0.3%. A class E power amplifier is designed with an efficiency of 72.9%, a transmit power of 3.1 W, and a gain of 31.8 dB. Furthermore, this reports also presents a systematic design approach for amplifiers, which illustrate the core principles on which all the designs are based.Electrical Engineering BA
Paul M Furth - One of the best experts on this subject based on the ideXlab platform.
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high performance voltage folLower with very Low Output Resistance for wta applications
IEICE Electronics Express, 2014Co-Authors: Ivan Padillacantoya, Paul M FurthAbstract:A modification of the conventional Flipped Voltage FolLower (FVF) to enhance its Output Resistance is presented. It consists of replacing the conventional cascoding transistor of the basic cell by a regulated cascode scheme. This decreases the Output Resistance by a factor gmro approximately, the gain of a transistor as an amplifying stage. This is achieved with only two additional transistors and a biasing current IB, offering a significant advantage with respect to other previously reported architectures that require considerably increased power consumption and number of devices. Simulation results in 0.5 µm technology show an enhancement factor of 16, approximately, with respect to the conventional FVF, resulting in an Output Resistance of 3.1 Ω. Additionally, the proposed folLower was implemented in a winner-take-all circuit to prove its functionality; simulation and experimental results confirm the proposed operation.
A Torralba - One of the best experts on this subject based on the ideXlab platform.
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bandwidth enhanced high current efficiency class ab buffer with very Low Output Resistance
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2018Co-Authors: Anindita Paul, Jaime Ramirezangulo, A TorralbaAbstract:A class-AB buffer with factor five Output current enhancement and 11 times higher bandwidth than a conventional buffer with comparable power dissipation is proposed. The Output impedance is Lower than $ {1~\Omega }$ . Experimental results of a test chip prototype fabricated in 0.18- ${\mu }\text{m}$ CMOS technology validate the proposed circuit.
