The Experts below are selected from a list of 112125 Experts worldwide ranked by ideXlab platform
Kwyro Lee - One of the best experts on this subject based on the ideXlab platform.
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a 50 300 mhz highly linear and low Noise cmos gm hbox c filter adopting multiple gated transistors for digital tv tuner ics
IEEE Transactions on Microwave Theory and Techniques, 2009Co-Authors: Kuduck Kwon, Hongteuk Kim, Kwyro LeeAbstract:In this paper, a highly linear and low Noise CMOS active tracking low-pass filter is presented to overcome a local oscillator harmonic mixing problem for Advanced Television Systems Committee terrestrial and cable digital TV tuner integrated circuits. A transconductor linearization technique based on a method of multiple gated transistors is adopted to improve the linearity performance. The cutoff frequency of the proposed filter is tunable from 50 to 300 MHz. Fabricated in a 0.18-mum CMOS process, the filter provides a minimum input referred Noise Density of 5 nV/radic(Hz) and maximum in-band output referred third-order intercept point of 16.9 dBm, while drawing an average current of 40 mA from 1.8 V. The total chip area is 1 mm times 0.9 mm.
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design methodology of baseband analog chain to maximize a spurious free dynamic range for atsc terrestrial and cable digital tv tuner
IEEE Transactions on Consumer Electronics, 2008Co-Authors: Kuduck Kwon, Hongteuk Kim, Kwyro LeeAbstract:This paper presents a fully integrated tunable CMOS baseband analog (BBA) chain optimized for advanced television systems committee (ATSC) terrestrial and cable digital TV tuner integrated circuits (ICs). To maximize the spurious free dynamic range (SFDR) of the BBA chain for both standards, the design guideline is introduced with respect to the optimized allocation of the gain of each block. The bandwidth is selectable from 3 MHz, 3.5 MHz, or 4 MHz. Fabricated in a 0.18-mum CMOS process, it provides a minimum input referred Noise Density of 15.5 nV/radic(Hz) with 62 dB gain and out-of-channel output referred third-order intercept point (OIP3) of 33 dBm, while it drains an average current of 89 mA from 3.3 V. The total chip area is 1 mm times 1.2 mm.
Tzuchun Chou - One of the best experts on this subject based on the ideXlab platform.
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denoising of salt and pepper Noise corrupted image using modified directional weighted median filter
Pattern Recognition Letters, 2012Co-Authors: Tzuchun ChouAbstract:Many denoising algorithms have been proposed to recover a Noise corrupted image. However, most of them cannot well recover a heavy Noise corrupted image with Noise Density above 70%. In this Letter, we propose a new approach to efficiently remove background Noise by detecting and modifying noisy pixels in an image. If the center pixel of a local window is classified to noisy, this center pixel is replaced by a weighted median value on an optimum direction, enabling impulse Noise to be removed. Conversely, the center pixel is kept unchanged when it is classified to Noise-free, yielding the quality of restored image being well maintained. Experimental results show that the proposed approach cannot only efficiently suppress high-Density impulse Noise, but also can well preserve the detailed information of an image.
Honglin Xu - One of the best experts on this subject based on the ideXlab platform.
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a closed loop sigma delta interface for a high q micromechanical capacitive accelerometer with 200 ng surd hz input Noise Density
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Honglin XuAbstract:In this paper, a fully-differential high-order switched-capacitor (SC) sigma-delta $(\Sigma\Delta)$ interface in a standard 0.5 $\mu{\hbox{m}}$ CMOS technology for a micromechanical capacitive accelerometer is presented. A 1 bit digital output is attained by the interface circuit based on a low-Noise front-end and a back-end third-order SC $\Sigma\Delta$ modulator, avoiding the use of a separate high-resolution $\Sigma\Delta$ converter to digitize the analog feedback signal. In addition, a micromechanical capacitive sensor element with a high quality factor (high-Q) is used to achieve high-resolution. Furthermore, closed-loop operation and electrical compensation are employed for damping the high-Q to ensure the stability of the high-order system. The sensor consumes 23 mW of power from a single 7 V supply at a sampling clock of 250 kHz. Meanwhile, a sensitivity of 1.896 V/g is achieved with a Noise floor of lower than 200 ng $/\surd$ Hz in low-frequency. The sensor has a nonlinearity of 0.15% with an input range of $\pm$ 1.2g. The bandwidth (BW) is 300 Hz and the bias instability is 18 $\mu\hbox{g}$ .
An Ping Qiu - One of the best experts on this subject based on the ideXlab platform.
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a 0 23 mu text g bias instability and 1 mu text g surd hz acceleration Noise Density silicon oscillating accelerometer with embedded frequency to digital converter in pll
IEEE Journal of Solid-state Circuits, 2017Co-Authors: Jian Zhao, Xi Wang, Yang Zhao, Guo Ming Xia, An Ping QiuAbstract:This paper presents a silicon oscillating accelerometer (SOA) with a new CMOS readout circuit architecture. A phase lock loop (PLL) with a hybrid and antiNoise folding PFD is employed to sustain the oscillation of the MEMS oscillator, and the oscillation amplitude is set by an external reference. In addition, a sigma-delta frequency-to-digital converter is combined with the PLL to digitize the accelerometer’s frequency output for low power consumption. The MEMS transducer and the readout circuit are fabricated in an 80- $\mu \text{m}$ SOI and standard 0.35- $\mu \text{m}$ CMOS process, respectively. The SOA achieves 0.23- $\mu \text{g}$ bias instability and 1- $\mu \text{g}$ /Hz $^{1/2}$ acceleration Noise Density with a ±30 g full-scale, which are equivalent to 4-ppb relative instability and 17-ppb/Hz $^{1/2}$ relative acceleration Noise Density. It only consumes 2.7 mW under a 1.5 V supply.
Kari Halonen - One of the best experts on this subject based on the ideXlab platform.
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Analog baseband chain of synthetic aperture radar (SAR) receiver
Analog Integrated Circuits and Signal Processing, 2013Co-Authors: Faizah Abu Bakar, Ville Saari, Qaiser Nehal, Pekka Ukkonen, Kari HalonenAbstract:An analog baseband chain for a synthetic aperture radar receiver implemented in a 130 nm CMOS technology is presented in this paper. Occupying 0.23 mm^2 of silicon area, the baseband chain consists of a three-stage variable gain amplifier (VGA), a 5th-order gm-C low-pass filter (LPF) and an output buffer. The gain of the chain can be controlled by tuning the control voltages of the VGA and has a range from 25 to 34 dB. 8 dB of the gain is embedded into the LPF. The bandwidth of the LPF is programmable from 100 to 190 MHz by means of capacitor matrices. The chain, which uses a 1.2 V supply voltage, achieves an input-referred Noise Density of 4 nV/ $$ \sqrt {\text{Hz}} $$ and an in-band IIP3 of −46 dBV rms.
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a 190mhz 4nv hz analog baseband chain of synthetic aperture radar sar receiver
NORCHIP, 2010Co-Authors: Faizah Abu Bakar, Qaiser Nehal, Ville Saari, Pekka Ukkonen, Kari HalonenAbstract:An analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology is presented in this paper. Occupying 0.23mm2 of silicon area, the baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF) and an Output Buffer (OBUF). The gain of the chain can be controlled by tuning the control voltages of the VGA and has a range from 25dB to 34dB. In addition, the LPF has an 8dB gain to meet the required dynamic range of the following block. The bandwidth of the LPF is programmable from 120MHz to 190MHz by means of capacitor matrices. The chain, which uses a 1.2V supply voltage, achieves 4nV/√Hz of input-referred Noise Density and −42dBV in-band IIP3.