The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform
K. Kinoshita - One of the best experts on this subject based on the ideXlab platform.
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Asian Test Symposium - Partially parallel scan chain for test length reduction by using retiming technique
Proceedings of the Fifth Asian Test Symposium (ATS'96), 1996Co-Authors: Y. Higami, S. Kajihara, K. KinoshitaAbstract:This paper presents a design-for-testability technique aimed at test length reduction for scan designed Circuits. A new concept, called partially parallel scan chain, is introduced. In the partially parallel scan chain, some flip-flops are arranged in parallel so that the number of scan shift clocks is reduced. Retiming techniques are used to select the flip-flops arranged in parallel. The flip-flops are repositioned only during test vector generation, but not actually. Then the test vectors generated for the retimed Circuit are applied to the Original Circuit. In this paper, the difference in detectability of faults between the retimed Circuit and the Original Circuit is also discussed. Finally experimental results are shown.
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Partially parallel scan chain for test length reduction by using retiming technique
Proceedings of the Fifth Asian Test Symposium (ATS'96), 1996Co-Authors: Y. Higami, S. Kajihara, K. KinoshitaAbstract:This paper presents a design-for-testability technique aimed at test length reduction for scan designed Circuits. A new concept, called partially parallel scan chain, is introduced. In the partially parallel scan chain, some flip-flops are arranged in parallel so that the number of scan shift clocks is reduced. Retiming techniques are used to select the flip-flops arranged in parallel. The flip-flops are repositioned only during test vector generation, but not actually. Then the test vectors generated for the retimed Circuit are applied to the Original Circuit. In this paper, the difference in detectability of faults between the retimed Circuit and the Original Circuit is also discussed. Finally experimental results are shown.
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VTS - Resynthesis for sequential Circuits designed with a specified initial state
Proceedings 13th IEEE VLSI Test Symposium, 1995Co-Authors: H. Yotsuyanagi, S. Kajihara, K. KinoshitaAbstract:This paper presents a retiming and redundancy removal method for a sequential Circuit with a specified initial state so that the resynthesized Circuit has a state corresponding to the initial state and gives same behavior for any input sequences of the Original Circuit. Experimental results show the proposed method can optimize Circuits as well as the method which does not consider the specified initial state.
S.k. Nandy - One of the best experts on this subject based on the ideXlab platform.
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Controller redesign based clock and register power minimization
2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000Co-Authors: S.k. NandyAbstract:Clock gating is an effective technique for minimizing dynamic power in sequential Circuits. However, clock gating has some practical difficulties viz., possibility of glitches on the gated clock and in use of static timing analysis for verifying timing of the design. In this paper we describe a robust scheme for power minimization that eliminates these difficulties of clock gating and yet provides nearly the same power savings. This scheme does not rely on propagation delays in the Circuit for functioning, and is robust across process technologies. In this scheme, the controllers sequencing operations in a datapath are modified so that the control signals themselves are used as clocks for registers in the datapath. Since these "control clocks" typically operate at lower frequencies, power is saved in the registers and in the clock drivers. This scheme also preserves the cycle boundaries on which registers in the Original Circuit load data, thereby allowing reuse of test cases developed for the functional verification of the Original Circuit.
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ISCAS - Controller redesign based clock and register power minimization
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000Co-Authors: S.k. NandyAbstract:Clock gating is an effective technique for minimizing dynamic power in sequential Circuits. However, clock gating has some practical difficulties viz., possibility of glitches on the gated clock and in use of static timing analysis for verifying timing of the design. In this paper we describe a robust scheme for power minimization that eliminates these difficulties of clock gating and yet provides nearly the same power savings. This scheme does not rely on propagation delays in the Circuit for functioning, and is robust across process technologies. In this scheme, the controllers sequencing operations in a datapath are modified so that the control signals themselves are used as clocks for registers in the datapath. Since these "control clocks" typically operate at lower frequencies, power is saved in the registers and in the clock drivers. This scheme also preserves the cycle boundaries on which registers in the Original Circuit load data, thereby allowing reuse of test cases developed for the functional verification of the Original Circuit.
Hans-joachim Wunderlich - One of the best experts on this subject based on the ideXlab platform.
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DFTS - SAT-based code synthesis for fault-secure Circuits
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2013Co-Authors: Atefe Dalirsani, Michael A. Kochte, Hans-joachim WunderlichAbstract:This paper presents a novel method for synthesizing fault-secure Circuits based on parity codes over groups of Circuit outputs. The fault-secure Circuit is able to detect all errors resulting from combinational and transition faults at a single node. The Original Circuit is not modified. If the Original Circuit is non-redundant, the result is a totally self-checking Circuit. At first, the method creates the minimum number of parity groups such that the effect of each fault is not masked in at least one parity group. To ensure fault-secureness, the obtained groups are split such that no fault leads to silent data corruption. This is performed by a formal Boolean satisfiability (SAT) based analysis. Since the proposed method reduces the number of required parity groups, the number of two-rail checkers and the complexity of the prediction logic required for fault-secureness decreases as well. Experimental results show that the area overhead is much less compared to duplication and less in comparison to previous methods for synthesis of totally self-checking Circuits. Since the Original Circuit is not modified, the method can be applied for fixed hard macros and IP cores.
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SAT-based code synthesis for fault-secure Circuits
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 2013Co-Authors: Atefe Dalirsani, Michael A. Kochte, Hans-joachim WunderlichAbstract:This paper presents a novel method for synthesizing fault-secure Circuits based on parity codes over groups of Circuit outputs. The fault-secure Circuit is able to detect all errors resulting from combinational and transition faults at a single node. The Original Circuit is not modified. If the Original Circuit is non-redundant, the result is a totally self-checking Circuit. At first, the method creates the minimum number of parity groups such that the effect of each fault is not masked in at least one parity group. To ensure fault-secureness, the obtained groups are split such that no fault leads to silent data corruption. This is performed by a formal Boolean satisfiability (SAT) based analysis. Since the proposed method reduces the number of required parity groups, the number of two-rail checkers and the complexity of the prediction logic required for fault-secureness decreases as well. Experimental results show that the area overhead is much less compared to duplication and less in comparison to previous methods for synthesis of totally self-checking Circuits. Since the Original Circuit is not modified, the method can be applied for fixed hard macros and IP cores.
Muhammad Shafique - One of the best experts on this subject based on the ideXlab platform.
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TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint
2019 Design Automation & Test in Europe Conference & Exhibition (DATE), 2019Co-Authors: Imran Hafeez Abbassi, Faiq Khalid, Semeen Rehman, Awais Mehmood Kamboh, Axel Jantsch, Siddharth Garg, Muhammad ShafiqueAbstract:Conventional Hardware Trojan (HT) detection techniques are based on the validation of integrated Circuits to determine changes in their functionality, and on non-invasive side-channel analysis to identify the variations in their physical parameters. In particular, almost all the proposed side-channel power-based detection techniques presume that HTs are detectable because they only add gates to the Original Circuit with a noticeable increase in power consumption. This paper demonstrates how undetectable HTs can be realized with zero impact on the power and area footprint of the Original Circuit. Towards this, we propose a novel concept of TrojanZero and a systematic methodology for designing undetectable HTs in the Circuits, which conceals their existence by gate-level modifications. The crux is to salvage the cost of the HT from the Original Circuit without being detected using standard testing techniques. Our methodology leverages the knowledge of transition probabilities of the Circuit nodes to identify and safely remove expendable gates, and embeds malicious Circuitry at the appropriate locations with zero power and area overheads when compared to the Original Circuit. We synthesize these designs and then embed in multiple ISCAS85 benchmarks using a 65nm technology library, and perform a comprehensive power and area characterization. Our experimental results demonstrate that the proposed TrojanZero designs are undetectable by the state-of-the-art power-based detection methods.
S.m. Reddy - One of the best experts on this subject based on the ideXlab platform.
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On masking of redundant faults in synchronous sequential Circuits with design-for-testability logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2005Co-Authors: I. Pomeranz, S.m. ReddyAbstract:Design for testability (DFT) for synchronous sequential Circuits causes redundant faults in the Original Circuit to be detectable in the Circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. In this paper, we propose to deal with such faults by masking (or ignoring) their fault effects when they appear on the Circuit outputs. This should be done without masking the detection of other faults of the Original Circuit, which need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the Original Circuit under a given test set generated for the Circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of masked faults among the faults that should be detected.
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on application of output masking to undetectable faults in synchronous sequential Circuits with design for testability logic
International Conference on Computer Aided Design, 2003Co-Authors: I. Pomeranz, S.m. ReddyAbstract:Design-for-testability (DFT) for synchronous sequential Circuits causes redundant faults in the Original Circuit to be detectable in the Circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. One way to deal with such faults is to mask (or ignore) their fault effects when they appear on the Circuit outputs, without masking the detection of faults that need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the Original Circuit under a given test set generated for the Circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of other masked faults.
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ICCAD - On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic
2003Co-Authors: I. Pomeranz, S.m. ReddyAbstract:Design-for-testability (DFT) for synchronous sequential Circuits causes redundant faults in the Original Circuit to be detectable in the Circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. One way to deal with such faults is to mask (or ignore) their fault effects when they appear on the Circuit outputs, without masking the detection of faults that need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the Original Circuit under a given test set generated for the Circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of other masked faults.
