The Experts below are selected from a list of 279 Experts worldwide ranked by ideXlab platform
Michael Nicolaidis - One of the best experts on this subject based on the ideXlab platform.
-
DATE - A CAD framework for generating Self-Checking multipliers based on residue codes
Proceedings of the conference on Design automation and test in Europe - DATE '99, 1999Co-Authors: I. Alzaher Noufal, Michael NicolaidisAbstract:The basic drawbacks related to the design of Self-Checking circuits include high hardware cost and design effort. Recent developments on Self-Checking operators based on parity prediction compatible schemes allow us to achieve high fault coverage and low hardware cost in Self-Checking data paths for the majority of basic data path blocks such as, adders, ALUs, shifters, register files, etc. However, parity prediction Self-Checking multipliers involve hardware overhead significantly higher than for other blocks. Thus, large multipliers will increase significantly the hardware overhead of the whole data path. Residue arithmetic codes allow to reduce this cost The tools presented in this paper generate automatically Self-Checking multipliers using such codes. They complete our tools using parity prediction for various other blocks, and enable automatic generation of low cost Self-Checking data paths.
-
Efficient Totally Self-Checking Shifter Design
Journal of Electronic Testing, 1998Co-Authors: R. O. Duarte, Michael Nicolaidis, H. Bederr, Yervant ZorianAbstract:Self-Checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This work is aimed to reach these requirements for the design of Self-Checking shifters and is part of a broader project concerning the design of Self-Checking data paths.
-
A CAD framework for efficient Self-Checking data path design
1997Co-Authors: R. Oliveira Duarte, I. Alzaher-noufal, Michael NicolaidisAbstract:The basic drawbacks related to the design of Self-Checking circuits include high hardware cost and high design efforts. Recent developments on Self-Checking operators based on parity prediction compatible schemes allow us to achieve high fault coverage and low hardware costs. The integration of these schemes in a dedicated CAD tool allows automatic generation, thus it reduces design efforts and makes Self-Checking circuits very attractive.
-
VTS - A tool for automatic generation of Self-Checking data paths
Proceedings 13th IEEE VLSI Test Symposium, 1995Co-Authors: B. Hamdi, H. Bederr, Michael NicolaidisAbstract:An important drawback of implementing Self-Checking circuits concerns the lack of dedicated CAD tools. This problem results on a significant increasing of the design effort and compromises the interest of such designs. CAD tools aimed to implement Self-Checking data paths is of high interest since data-paths are basic parts of microprocessors and microcontrollers. The tools presented here include generators of Self-Checking adders, ALUs, multipliers, dividers, shifters and register files, as well as generators of parity and double rail checkers. Another tool interconnects these blocks to generate the Self-Checking data-path.
-
EDAC-ETC-EUROASIC - Efficient implementations of Self-Checking multiply and divide arrays
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC, 1994Co-Authors: Michael Nicolaidis, H. BederrAbstract:In this paper we present efficient self checking implementations for multiply and divide arrays. These implementations are strongly fault secure or totally Self-Checking for a comprehensive fault model which includes stuck-at, stuck-on and stuck-open faults. They are compatible with data paths checked by the parity code (i.e. no code translators are needed), so that the self checking implementation of the whole data path is simplified. >
P K Lala - One of the best experts on this subject based on the ideXlab platform.
-
A technique for modular design of Self-Checking carry-select adder
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05), 2005Co-Authors: D.p. Vasudevan, P K LalaAbstract:The carry-select adders provide significant speed improvement over other types of adders. This paper proposes a new approach for constructing Self-Checking carry-select adders set of faults online. Adders of arbitrary size can be constructed by simply cascading the appropriate number of 2-bit adders. A range of adders from 4 bit to 128 bits was designed using this approach employing a 0.5/spl mu/m CMOS technology. The area needed for implementing the Self-Checking adders is 16.07 % to 20.67% more than that required in adders without built-in Self-Checking capability.
-
On Self-Checking Design ofCMOS Circuits for Multiple Faults
1998Co-Authors: Fadi Busaba, P K Lala, Alvernon WalkerAbstract:A technique for designing totally Self-Checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally Self-Checking. Experiemntal results show the overhead, delay and power consumption for the proposed technique. This paper also presents a technique for designing multistage TSC FCMOS circuits.
-
On Self-Checking Design of CMOS Circuits for Multiple Faults
Vlsi Design, 1998Co-Authors: Fadi Busaba, P K Lala, Alvernon WalkerAbstract:A technique for designing totally Self-Checking (TSC) FCMOS (Fully Complementary MOS) designs for multiple faults is presented in this paper. The existing techniques for self checking design consider only single faults, and suffer from high silicon area overhead. The multiple faults considered in this paper are multiple breaks, multiple transistors stuck-offs and multiple transistors stuck-ons. Starting from FCMOS design, small modifications (addition of two-weak transistors) make the original circuit totally Self-Checking. Experiemntal results show the overhead, delay and power consumption for the proposed technique. This paper also presents a technique for designing multistage TSC FCMOS circuits.
-
self checking and fault tolerant digital design
1995Co-Authors: P K LalaAbstract:Chapter 1 - Fundamentals of Reliability Chapter 2 - Error Detecting and Correcting Codes Chapter 3 - Self-Checking Combinational Logic Design Chapter 4 - Self-Checking Checkers Chapter 5 - Self-Checking Sequential Circuit Design Chapter 6 - Fault-Tolerant Design Appendix Markov Models
-
On Self-Checking software design
IEEE Proceedings of the SOUTHEASTCON '91, 1991Co-Authors: P K Lala, K.c. YarlagaddaAbstract:The authors explain problems due to faults in software and suggest techniques based on the concept of Self-Checking for increasing fault-tolerance in software design. The goal of Self-Checking is to guarantee that the erroneous output of a circuit is not a valid codeword if there is a fault, permanent or transient, in the circuit, or if the circuit receives a noncodeword. Extending the concept to the software module level would mean having the ability to determine online whether the output data produced by the module meet the module's output specifications. As the concept of Self-Checking software is logically the same as that of hardware, various hardware approaches should be extensible to software. Emphasis should be placed on developing a set of standards for normal behavior which will enhance Self-Checking capability and on evaluating the cost-effectiveness of different Self-Checking techniques, with the objective of developing a formal methodology for implementing Self-Checking software systems.
Cecilia Metra - One of the best experts on this subject based on the ideXlab platform.
-
Self-Checking Voter for High Speed TMR Systems
Journal of Electronic Testing, 2005Co-Authors: José Manuel Cazeaux, Daniele Rossi, Cecilia MetraAbstract:In this paper we address the problem of faults possibly affecting voters of TMR systems and making them provide incorrect majority data, thus making the adoption of the TMR technique useless. We consequently instantiate the need for Self-Checking voting schemes and propose a new CMOS Self-Checking voter that, compared to alternate Self-Checking solutions, features the advantage of being faster, while requiring comparable power consumption and a small increase in area overhead.
-
IOLTS - New high speed CMOS Self-Checking voter
2004Co-Authors: José Manuel Cazeaux, Daniele Rossi, Cecilia MetraAbstract:Faults possibly affecting voters of TMR (triple modular redundancy) systems, employed in high reliability applications, can make them provide the fan-out logic with incorrect data, hence making the adoption of the TMR technique useless. In this paper we instantiate the need for Self-Checking voters and we propose a new Self-Checking voting scheme that, compared to alternate Self-Checking solutions, features the advantage of being faster, while requiring comparable power consumption. This is achieved at the cost of a small increase in area overhead.
-
DATE - On the design of Self-Checking functional units based on Shannon circuits
Proceedings of the conference on Design automation and test in Europe - DATE '99, 1999Co-Authors: M. Favalli, Cecilia MetraAbstract:This paper investigates the application of Shannon (BDD) circuits, that feature interesting low-power capabilities, to the design of Self-Checking functional units. A technique is proposed that, by using a time redundancy approach, makes this kind of circuits totally Self-Checking with respect to stuck-at-faults. For a set of possibly used pass-transistor-based CMOS implementations, we show that the totally Self-Checking or the strongly fault secure properties hold for a wider set of realistic faults, including transistors stuck-open/on and bridgings.
-
Concurrent checking of clock signal correctness
IEEE Design & Test of Computers, 1998Co-Authors: Cecilia Metra, M. Favalli, Bruno RiccoAbstract:Traditional concurrent-checking techniques may not detect the occurrence of the transient faults and resulting errors likely to affect clock signals in VLSI systems. The authors present a new method and Self-Checking circuit implementation for concurrently checking the correctness of clock distribution network signals in synchronous systems.
M. Nicolaidis - One of the best experts on this subject based on the ideXlab platform.
-
A CAD framework for generating Self-Checking multipliers based on residue codes
1999Co-Authors: I. Alzaher-noufal, M. NicolaidisAbstract:The basic drawbacks related to the design of Self-Checking circuits include high hardware cost and design effort. Recent developments on Self-Checking operators based on parity prediction compatible schemes allow us to achieve high fault coverage and low hardware cost in Self-Checking data paths for the majority of basic data path blocks such as, adders, ALUs, shifters, register files, etc. However, parity prediction Self-Checking multipliers involve hardware overhead significantly higher than for other blocks. Thus, large multipliers will increase significantly the hardware overhead of the whole data path. Residue arithmetic codes allow to reduce this cost The tools presented in this paper generate automatically Self-Checking multipliers using such codes. They complete our tools using parity prediction for various other blocks, and enable automatic generation of low cost Self-Checking data paths.
-
Efficient Totally Self-Checking Shifter Design
On-Line Testing for VLSI, 1998Co-Authors: R. O. Duarte, M. Nicolaidis, H. Bederr, Yervant ZorianAbstract:International audienceSelf-Checking designs will gain increasing interest in industrial applications if they satisfy the following requirements: high fault coverage, reduced hardware cost and reduced design effort. This work is aimed to reach these requirements for the design of Self-Checking shifters and is part of a broader project concerning the design of Self-Checking data paths
-
Finitely Self-Checking circuits and their application on current sensors
Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium, 1993Co-Authors: M. NicolaidisAbstract:The theory of digital Self-Checking circuits has been developed in order to make formal the techniques of designing digital circuits allowing one to ensure on-line concurrent error detection. In recent years analog and mixed signal circuits have gained importance and represent a relevant part of the products of the integrated circuits industry. The design of Self-Checking analog and mixed signals circuits is a potential solution in order to achieve the reliability of systems using such circuits. Thus, establishing the Self-Checking theory for analog and mixed signal circuits will allow one to make the design of such circuits formal, and is of great importance. This paper proposes the basic theory of Self-Checking analog and mixed signal circuits and applies this theory to the case of current checkers which should become in the future an important element for high quality manufacturing, testing and on-line concurrent error detection.
-
Design of static CMOS Self-Checking circuits using built-in current sensing
[1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing, 1992Co-Authors: J.-c. Lo, J.c. Daly, M. NicolaidisAbstract:The authors present a novel scheme for implementing Self-Checking circuits in static CMOS. A strongly code disjoint (SCD) built-in current sensor (BICS) is presented. It is used to cover faults whose detection cannot be guaranteed by logic monitoring. A previously fabricated and tested high-speed BICS is examined for its behavior in the presence of faults. Then, a self-exercising mechanism is designed to obtain the SCD property. The integration of this SCD BICS with a Self-Checking circuit achieves the well-known goal of total Self-Checking.
-
Shorts in Self-Checking circuits
Journal of Electronic Testing, 1991Co-Authors: M. NicolaidisAbstract:It has been noted by several authors that the classical stuck-at logical fault model might not be an appropriate representation of certain real failures occurring in integrated circuits. Shorts are an important class of such faults. This article gives a detailed analysis of the effects of shorts in Self-Checking circuits and proposes techniques for dealing with them. More precisely, we show that, unlike other faults such as stuck-at, stuck-on, and stuck-open—which produce only single errors in the place they occur—shorts can produce double errors on the two shorted lines. In particular, feedback shorts can produce double errors on the two shorted lines. The double error is unidirectional for some feedback shorts and non-unidirectional for some others. Furthermore, in some technologies (e.g., CMOS), non-feedback shorts can also produce double non-unidirectional errors. We also show that unlike stuck-at, stuck-on, and stuck-open faults, redundant shorts can destroy the SFS property. Then we propose several techniques for coping with these problems and we illustrate the results by circuit implementation examples. The present study is given for NMOS and CMOS circuits but we show that it is valid for any other technology.
J.p. Parkerson - One of the best experts on this subject based on the ideXlab platform.
-
A technique for designing totally Self-Checking domino logic circuits
Sixth international symposium on quality electronic design (isqed'05), 2005Co-Authors: C.k. Tang, P.k. Lata, J.p. ParkersonAbstract:A scheme for concurrent Self-Checking domino logic circuit is proposed. The Self-Checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function. A checker circuit is embedded into the Self-Checking implementation. The scheme is especially suitable for large CMOS domino logic circuits.
-
ISQED - A technique for designing totally Self-Checking domino logic circuits
Sixth International Symposium on Quality of Electronic Design (ISQED'05), 2005Co-Authors: C.k. Tang, P.k. Lata, J.p. ParkersonAbstract:A scheme for concurrent Self-Checking domino logic circuit is proposed. The Self-Checking feature is achieved by transistor sharing of the original and its inverse functions and by using the outputs as 1-out-of-2 code. The sharing of transistors lowers the overhead required for the inverse function. A checker circuit is embedded into the Self-Checking implementation. The scheme is especially suitable for large CMOS domino logic circuits.
