Oversampling Ratio

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Terri S. Fiez - One of the best experts on this subject based on the ideXlab platform.

  • a low Oversampling Ratio 14 b 500 khz spl delta spl sigma adc with a self calibrated multibit dac
    IEEE Journal of Solid-state Circuits, 1996
    Co-Authors: R.t. Baird, Terri S. Fiez
    Abstract:

    Delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADC's) rely on Oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced Oversampling requirements is developed. A 14-bit 500-kHz /spl Delta//spl Sigma/ ADC is described that uses an Oversampling Ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-/spl mu/m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and Oversampling Ratio of 16. This is the lowest Oversampling Ratio for this resolution and bandwidth achieved to date.

  • A low Oversampling Ratio 14-b 500-kHz /spl Delta//spl Sigma/ ADC with a self-calibrated multibit DAC
    IEEE Journal of Solid-State Circuits, 1996
    Co-Authors: R.t. Baird, Terri S. Fiez
    Abstract:

    Delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADC's) rely on Oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced Oversampling requirements is developed. A 14-bit 500-kHz /spl Delta//spl Sigma/ ADC is described that uses an Oversampling Ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-/spl mu/m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and Oversampling Ratio of 16. This is the lowest Oversampling Ratio for this resolution and bandwidth achieved to date.

  • versampling Ratio 14-b 500-kHz AX a Self-calibrated Multibit DAC
    1996
    Co-Authors: R.t. Baird, Terri S. Fiez
    Abstract:

    Delta-sigma (AX) analog-to-digital converters (ADC's) rely on Oversampling to achieve high-resolution. By applying multibit quantization to overcom stability limitations, a circuit topology with greatly reduced Oversampling requirements is developed. A 14-bit 500-kHz AX ADC is described that uses an Oversampling Ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-pm CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and Oversampling Ratio of 16. This is the lowest Oversampling Ratio for this resolution and bandwidth achieved to date.

R.t. Baird - One of the best experts on this subject based on the ideXlab platform.

  • a low Oversampling Ratio 14 b 500 khz spl delta spl sigma adc with a self calibrated multibit dac
    IEEE Journal of Solid-state Circuits, 1996
    Co-Authors: R.t. Baird, Terri S. Fiez
    Abstract:

    Delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADC's) rely on Oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced Oversampling requirements is developed. A 14-bit 500-kHz /spl Delta//spl Sigma/ ADC is described that uses an Oversampling Ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-/spl mu/m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and Oversampling Ratio of 16. This is the lowest Oversampling Ratio for this resolution and bandwidth achieved to date.

  • A low Oversampling Ratio 14-b 500-kHz /spl Delta//spl Sigma/ ADC with a self-calibrated multibit DAC
    IEEE Journal of Solid-State Circuits, 1996
    Co-Authors: R.t. Baird, Terri S. Fiez
    Abstract:

    Delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converters (ADC's) rely on Oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced Oversampling requirements is developed. A 14-bit 500-kHz /spl Delta//spl Sigma/ ADC is described that uses an Oversampling Ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-/spl mu/m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and Oversampling Ratio of 16. This is the lowest Oversampling Ratio for this resolution and bandwidth achieved to date.

  • versampling Ratio 14-b 500-kHz AX a Self-calibrated Multibit DAC
    1996
    Co-Authors: R.t. Baird, Terri S. Fiez
    Abstract:

    Delta-sigma (AX) analog-to-digital converters (ADC's) rely on Oversampling to achieve high-resolution. By applying multibit quantization to overcom stability limitations, a circuit topology with greatly reduced Oversampling requirements is developed. A 14-bit 500-kHz AX ADC is described that uses an Oversampling Ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-pm CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and Oversampling Ratio of 16. This is the lowest Oversampling Ratio for this resolution and bandwidth achieved to date.

Manoj Sachdev - One of the best experts on this subject based on the ideXlab platform.

  • A 0.8V /spl Delta//spl Sigma/ modulator using DTMOS technique
    2005 IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: Mohammad Maymandi-nejad, Manoj Sachdev
    Abstract:

    A 0.8V second order /spl Delta//spl Sigma/ modulator is designed in 0.18 /spl mu/m bulk CMOS technology. The dynamic threshold MOSFET (DTMOS) technique is used to enhance the performance of the circuit building blocks at very low supply voltage. Schematic and post layout simulation results are provided. In case of the amplifier with the embedded CMFB, the measurement results are presented. The modulator can achieve a SNR of approximately 80dB with an Oversampling Ratio (OSR) of 200 and consumes a power of 460 /spl mu/W.

Ichiro Fujimori - One of the best experts on this subject based on the ideXlab platform.

  • a 90 db snr 2 5 mhz output rate adc using cascaded multibit delta sigma modulation at 8 spl times Oversampling Ratio
    IEEE Journal of Solid-state Circuits, 2000
    Co-Authors: Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Steve Kosic, Jun Cao, K Seiyama, Shulap Chan
    Abstract:

    A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8/spl times/ Oversampling Ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm/sup 2/ chip in 0.5-/spl mu/m CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise Ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation.

  • a 90 db snr 2 5 mhz output rate adc using cascaded multibit spl delta spl sigma modulation at 8x Oversampling Ratio
    International Solid-State Circuits Conference, 2000
    Co-Authors: Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Steve Kosic, Jun Cao, Shuiap Chan
    Abstract:

    This 16b, 2.5 MHz output rate ADC is intended for xDSL and high-speed instrumentation applications. A fourth-order cascaded /spl Delta//spl Sigma/ modulator (/spl Delta//spl Sigma/M) operating at 20 MHz employs multibit quantization and dynamic element matching (DEM) to make all quantization noise contributions negligible at an Oversampling Ratio (OSR) of eight. The ADC achieves 90 dB signal-to-noise Ratio (SNR) in a 1.25 MHz bandwidth, and 102 dB spurious free dynamic range (SFDR) with 270 mW dissipation.

Hannu Tenhunen - One of the best experts on this subject based on the ideXlab platform.

  • Nonlinear Quantization in Low Oversampling Ratio Sigma-Delta Noise Shapers for RF Applications
    Analog Integrated Circuits and Signal Processing, 2002
    Co-Authors: A Gothenberg, Hannu Tenhunen
    Abstract:

    Baseband signal processing for current base stations or 3rd geneRation mobile systems will impose high bandwidth and high VLSI integRation demand. Many of the desired integRation aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low Oversampling Ratio in order to achieve the desired baseband width. In this paper, we present system architecture results for the 4th-order cascaded noise shaper architectures to be used in baseband front-ends. We show that the cascaded structures with proper scaling will satisfy simultaneous demand on linearity (spurious free dynamic range) and high SQNR with low Oversampling Ratio based on usage of multibit quantizers outside the actual signal noise shaping path. We also present results for nonlinear quantization effects in low Oversampling Ratio cascaded noise shaper architectures. We analyse the effect of the non-linearity in both the A/D and D/A-block in quantization error quantizer path for the 4th-order cascaded topology and the design constraints associated to the performance of the used A/D and D/A structures. The performance requirement for the multi-bit quantizer for high SQNR is shown for the case of low Oversampling Ratios. The results show that non-uniform quantization around zero input are far more crucial to the SQNR than nonlinear quantization deviating from the ideal transfer function. As the key difference to standard multibit quantizers, no special error correction or error distribution schemes are required; the linearity requirements are satisfied with 0.2 LSB accuracy of the few bit quantizer. Finally, the performance of non-linear quantization using multitone test signals are also shown.

  • Improved cascaded sigma-delta noise shaper architecture with reduced sensitivity to circuit nonlinearities
    Electronics Letters, 2002
    Co-Authors: A Gothenberg, Hannu Tenhunen
    Abstract:

    An improved cascaded sigma-delta noise shaper with reduced sensitivity to switch and opamp nonlinearities is presented. The architecture can be used for wideband applications, i.e. RF-front ends, at low Oversampling Ratio, as well as for high-resolution audio applications.

  • performance analysis of low Oversampling Ratio sigma delta noise shapers for rf applications
    International Symposium on Circuits and Systems, 1998
    Co-Authors: A Gothenberg, Hannu Tenhunen
    Abstract:

    Baseband signal processing for current base stations or 3rd geneRation mobile systems will impose high bandwidth and high VLSI integRation demand. Many of the desired integRation aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low Oversampling Ratio in order to achieve the desired baseband width. In this paper, we present system architecture results for 4th-order cascaded noise shaper architectures for baseband front-ends and show that the cascaded structures with proper scaling will satisfy simultaneous demand on linearity (spurious free dynamic range) and high SQNR with low Oversampling Ratio based on usage of multibit quantizers outside the actual signal noise shaping path.

  • Fully differential CMOS sigma-delta modulator for high performance analog-to-digital conversion with 5 V operating voltage
    1988. IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: T. Ritoniemi, Hannu Tenhunen, T. Karema, M. Lindell
    Abstract:

    The authors present a high-performance second-order sigma-delta modulator for modem and ISDN (integrated-services digital network) analog-to-digital (A/D) conversion applications. The major performance design limiting factors are demonstrated. It is shown that a true 16-bit A/D converter with single 5-V power supply for voice band can be realized with an Oversampling Ratio of 512; and a 16-bit dynamic range is achieved with an Oversampling Ratio of 256. The die size of the proposed modulator, using 2.5- mu m CMOS technology, is only 0.56 mm/sup 2/. >

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