The Experts below are selected from a list of 40296 Experts worldwide ranked by ideXlab platform
Huazhong Yang - One of the best experts on this subject based on the ideXlab platform.
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nicslu an adaptive sparse matrix solver for Parallel Circuit simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013Co-Authors: Xiaoming Chen, Yu Wang, Huazhong YangAbstract:The sparse matrix solver has become a bottleneck in simulation program with integrated Circuit emphasis (SPICE)-like Circuit simulators. It is difficult to Parallelize the solver because of the high data dependency during the numeric LU factorization and the irregular structure of Circuit matrices. This paper proposes an adaptive sparse matrix solver called NICSLU, which uses a multithreaded Parallel LU factorization algorithm on shared-memory computers with multicore/multisocket central processing units to accelerate Circuit simulation. The solver can be used in all the SPICE-like Circuit simulators. A simple method is proposed to predict whether a matrix is suitable for Parallel factorization, such that each matrix can achieve optimal performance. The experimental results on 35 matrices reveal that NICSLU achieves speedups of 2.08× ~ 8.57×(on the geometric mean), compared with KLU, with 1-12 threads, for the matrices which are suitable for the Parallel algorithm. NICSLU can be downloaded from http://nicslu.weebly.com.
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sparse lu factorization for Parallel Circuit simulation on gpu
Design Automation Conference, 2012Co-Authors: Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, Huazhong YangAbstract:Sparse solver has become the bottleneck of SPICE simulators. There has been few work on GPU-based sparse solver because of the high data-dependency. The strong data-dependency determines that Parallel sparse LU factorization runs efficiently on shared-memory computing devices. But the number of CPU cores sharing the same memory is often limited. The state of the art Graphic Processing Units (GPU) naturally have numerous cores sharing the device memory, and provide a possible solution to the problem. In this paper, we propose a GPU-based sparse LU solver for Circuit simulation. We optimize the work partitioning, the number of active thread groups, and the memory access pattern, based on GPU architecture. On matrices whose factorization involves many floating-point operations, our GPU-based sparse LU factorization achieves 7.90× speedup over 1-core CPU and 1.49× speedup over 8-core CPU. We also analyze the scalability of Parallel sparse LU factorization and investigate the specifications on CPUs and GPUs that most influence the performance.
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an adaptive lu factorization algorithm for Parallel Circuit simulation
Asia and South Pacific Design Automation Conference, 2012Co-Authors: Xiaoming Chen, Yu Wang, Huazhong YangAbstract:Sparse matrix solver has become the bottleneck in SPICE simulator. It is difficult to Parallelize the solver because of the high data-dependency during the numerical LU factorization. This paper proposes a Parallel LU factorization (with partial pivoting) algorithm on shared-memory computers with multi-core CPUs, to accelerate Circuit simulation. Since not every matrix is suitable for Parallel algorithm, a predictive method is proposed to decide whether a matrix should use Parallel or sequential algorithm. The experimental results on 35 Circuit matrices reveal that the developed algorithm achieves speedups of 2.11×∼8.38× (on geometric-average), compared with KLU, with 1∼8 threads, on the matrices which are suitable for Parallel algorithm. Our solver can be downloaded from http://nicslu.weebly.com.
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DAC - Sparse LU factorization for Parallel Circuit simulation on GPU
Proceedings of the 49th Annual Design Automation Conference on - DAC '12, 2012Co-Authors: Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, Huazhong YangAbstract:Sparse solver has become the bottleneck of SPICE simulators. There has been few work on GPU-based sparse solver because of the high data-dependency. The strong data-dependency determines that Parallel sparse LU factorization runs efficiently on shared-memory computing devices. But the number of CPU cores sharing the same memory is often limited. The state of the art Graphic Processing Units (GPU) naturally have numerous cores sharing the device memory, and provide a possible solution to the problem. In this paper, we propose a GPU-based sparse LU solver for Circuit simulation. We optimize the work partitioning, the number of active thread groups, and the memory access pattern, based on GPU architecture. On matrices whose factorization involves many floating-point operations, our GPU-based sparse LU factorization achieves 7.90× speedup over 1-core CPU and 1.49× speedup over 8-core CPU. We also analyze the scalability of Parallel sparse LU factorization and investigate the specifications on CPUs and GPUs that most influence the performance.
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ASP-DAC - An adaptive LU factorization algorithm for Parallel Circuit simulation
17th Asia and South Pacific Design Automation Conference, 2012Co-Authors: Xiaoming Chen, Yu Wang, Huazhong YangAbstract:Sparse matrix solver has become the bottleneck in SPICE simulator. It is difficult to Parallelize the solver because of the high data-dependency during the numerical LU factorization. This paper proposes a Parallel LU factorization (with partial pivoting) algorithm on shared-memory computers with multi-core CPUs, to accelerate Circuit simulation. Since not every matrix is suitable for Parallel algorithm, a predictive method is proposed to decide whether a matrix should use Parallel or sequential algorithm. The experimental results on 35 Circuit matrices reveal that the developed algorithm achieves speedups of 2.11×∼8.38× (on geometric-average), compared with KLU, with 1∼8 threads, on the matrices which are suitable for Parallel algorithm. Our solver can be downloaded from http://nicslu.weebly.com.
Andrei Grebennikov - One of the best experts on this subject based on the ideXlab platform.
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An Extended Topology of Parallel-Circuit Class-E Power Amplifier to Account for Larger Output Capacitances
IEEE Transactions on Microwave Theory and Techniques, 2011Co-Authors: J. Cumana, Andrei Grebennikov, N Kumar, Guolin Sun, Rolf H. JansenAbstract:This paper presents a modified Parallel-Circuit class-E amplifier that accommodates devices with larger output capacitances, recovering the class-E operating conditions. The finite inductor in the Parallel Circuit topology is replaced by a more suitable network composed of a series inductor and additional subharmonic resonators. Analysis of the class-E amplifier allows to determine the required frequency-domain response of this new network. Derivation of the Circuit elements of the proposed network is shown in detail, and a design procedure for this modified class-E is provided. The analysis is validated by simulation and design of a test board. Measurements of the test board showed a drain efficiency of 80.7%, power-added efficiency of 78.6%, and output power of 4.91 W at 434 MHz, exhibiting levels of efficiency similar to that obtained by other amplifiers using the same device, but at much lower frequencies. According to the authors' knowledge, this study represents the first systematic approach to design class-E power amplifiers at UHF using devices with larger COUT by taking into account the use of arbitrary finite-feed class-E topologies.
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high efficiency broadband Parallel Circuit class e rf power amplifier with reactance compensation technique
IEEE Transactions on Microwave Theory and Techniques, 2008Co-Authors: N Kumar, Andrei Grebennikov, Chacko Prakash, Arturo MedianoAbstract:Class E amplifier offers high efficiency approaching 100% for an ideal case. This paper introduces a first practical implementation of a novel broadband class E power amplifier design combining a Parallel-Circuit load network with a reactance compensation technique. The novel broadband Parallel-Circuit class E load network using reactance compensation technique has been discussed based on theory and its experimental verification. A proper guidelines method of designing a high-efficiency broadband class E power amplifier with an LDMOS transistor until the final prototype measurement and optimization will be discussed. In the measurement level, the drain efficiency of 74% at an operating power of 8 W and power flatness of 0.7 dB are achieved across a bandwidth of 136-174 MHz. The efficiency result is the highest result for VHF broadband frequency to date with a low supply voltage of 7.2 V. Simulations of the efficiency, output power, drain voltage waveform, and load angle (impedance) were verified by measurements and good agreements were obtained.
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load network design techniques for class e rf and microwave amplifiers
2004Co-Authors: Andrei GrebennikovAbstract:Based on theoretical analysis, this article examines the required voltage and current waveforms, and Circuit parameters are determined for particular Circuits corresponding to: Class E with shunt capacitance, even harmonic Class E, Parallel-Circuit Class E, and Class E with quarter wave transmission line. The effect of the device output bondwire inductance on the optimum load network parameters is shown. The operating power gain achieved with the Parallel-Circuit Class E power amplifier is evaluated and compared with the operating power gain of the conventional Class B power amplifier. A load network implementation with matching Circuit using transmission line elements is considered with exact Circuit parameters. This article is generally complete, but is condensed from two longer papers that provide more in-depth discussion and development of the design equations and their implementations. Those papers, as well as this article, are available for downloading at this magazine’s web site.
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switched mode rf and microwave Parallel Circuit class e power amplifiers original articles
International Journal of Rf and Microwave Computer-aided Engineering, 2004Co-Authors: Andrei GrebennikovAbstract:The Parallel-Circuit Class E tuned power amplifiers with load networks consisting of either one capacitance and one inductor or a Parallel LC Circuit and series filter are described and analyzed. The elements of the load networks are defined using the same analytical approach with a set of the exact design equations. The ideal collector voltage and current waveforms for both configurations demonstrate a possible 100p efficiency and do not overlap. RF and microwave applications are demonstrated based on the simulation and experimental results of low-voltage InGaP/GaAs HBT and high-voltage LDMOSFET power amplifiers. These switched-mode Parallel-Circuit Class E power amplifiers offer a new challenge for RF and microwave power amplification by providing high-efficiency operating conditions. © 2003 Wiley Periodicals, Inc. Int J RF and Microwave CAE 14, 21–35, 2004.
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switched mode rf and microwave Parallel Circuit class e power amplifiers
International Journal of Rf and Microwave Computer-aided Engineering, 2004Co-Authors: Andrei GrebennikovAbstract:The Parallel-Circuit Class E tuned power amplifiers with load networks consisting of either one capacitance and one inductor or a Parallel LC Circuit and series filter are described and analyzed. The elements of the load networks are defined using the same analytical approach with a set of the exact design equations. The ideal collector voltage and current waveforms for both configurations demonstrate a possible 100% efficiency and do not overlap. RF and microwave applications are demonstrated based on the simulation and experimental results of low-voltage InGaP/GaAs HBT and high-voltage LDMOSFET power amplifiers. These switched-mode Parallel-Circuit Class E power amplifiers offer a new challenge for RF and microwave power amplification by providing high-efficiency operating conditions. © 2003 Wiley Periodicals, Inc. Int J RF and Microwave CAE 14, 21–35, 2004.
Yuepeng Yan - One of the best experts on this subject based on the ideXlab platform.
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An Extended Topology of Parallel-Circuit Class-E Power Amplifier Using Transmission-Line Compensation
IEEE Transactions on Microwave Theory and Techniques, 2013Co-Authors: Yongqing Leng, Yun Zeng, Lijun Zhang, Yatao Peng, Guoliang Zhang, Jin Guan, Yuepeng YanAbstract:This paper presents a Parallel-Circuit Class-E amplifier that maintains it operating characteristics even when the output capacitance of the transistor is greater than the optimum shunt capacitance. The finite dc feed inductor in the Parallel Circuit topology is replaced by a transmission-line compensation Circuit to eliminate the limitations on the operating frequency imposed by the output capacitance. Theoretical formulas for the Circuit elements of the proposed network are derived in detail, and the analysis is validated by simulation and measurement. The measured maximum output power of 40.1 dBm, drain efficiency of 77.5%, and power-added efficiency of 70.8% were obtained at 2.8 GHz with a 29.4-dBm input power. These measurements show a similar or better level of efficiency and output power that is reported for other amplifiers at lower frequencies using the same transistor.
Yongqing Leng - One of the best experts on this subject based on the ideXlab platform.
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An Extended Topology of Parallel-Circuit Class-E Power Amplifier Using Transmission-Line Compensation
IEEE Transactions on Microwave Theory and Techniques, 2013Co-Authors: Yongqing Leng, Yun Zeng, Lijun Zhang, Yatao Peng, Guoliang Zhang, Jin Guan, Yuepeng YanAbstract:This paper presents a Parallel-Circuit Class-E amplifier that maintains it operating characteristics even when the output capacitance of the transistor is greater than the optimum shunt capacitance. The finite dc feed inductor in the Parallel Circuit topology is replaced by a transmission-line compensation Circuit to eliminate the limitations on the operating frequency imposed by the output capacitance. Theoretical formulas for the Circuit elements of the proposed network are derived in detail, and the analysis is validated by simulation and measurement. The measured maximum output power of 40.1 dBm, drain efficiency of 77.5%, and power-added efficiency of 70.8% were obtained at 2.8 GHz with a 29.4-dBm input power. These measurements show a similar or better level of efficiency and output power that is reported for other amplifiers at lower frequencies using the same transistor.
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Transmission-line compensation Circuit of Parallel-Circuit class-E power amplifier to extend maximum operating frequency
Electronics Letters, 2012Co-Authors: Yongqing Leng, Yun Zeng, Lijun Zhang, Yatao Peng, Guoliang Zhang, Jin GuanAbstract:Presented is a modified Parallel-Circuit class-E amplifier that operates above the theoretical maximum frequency, recovering the class-E operating conditions. The finite inductor in the Parallel Circuit topology is replaced by a more suitable network composed of four transmission lines. The theory formula of the Circuit elements of the proposed network is derived in detail, and an example is designed and measured to validate the analysis. The measured maximum output power of 40 dBm, drain efficiency of 77.5%, and power-added efficiency of 70.8% at 2.8 GHz were obtained, showing excellent efficiency compared to that obtained by other amplifiers using the same device.
Xiaoming Chen - One of the best experts on this subject based on the ideXlab platform.
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nicslu an adaptive sparse matrix solver for Parallel Circuit simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013Co-Authors: Xiaoming Chen, Yu Wang, Huazhong YangAbstract:The sparse matrix solver has become a bottleneck in simulation program with integrated Circuit emphasis (SPICE)-like Circuit simulators. It is difficult to Parallelize the solver because of the high data dependency during the numeric LU factorization and the irregular structure of Circuit matrices. This paper proposes an adaptive sparse matrix solver called NICSLU, which uses a multithreaded Parallel LU factorization algorithm on shared-memory computers with multicore/multisocket central processing units to accelerate Circuit simulation. The solver can be used in all the SPICE-like Circuit simulators. A simple method is proposed to predict whether a matrix is suitable for Parallel factorization, such that each matrix can achieve optimal performance. The experimental results on 35 matrices reveal that NICSLU achieves speedups of 2.08× ~ 8.57×(on the geometric mean), compared with KLU, with 1-12 threads, for the matrices which are suitable for the Parallel algorithm. NICSLU can be downloaded from http://nicslu.weebly.com.
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sparse lu factorization for Parallel Circuit simulation on gpu
Design Automation Conference, 2012Co-Authors: Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, Huazhong YangAbstract:Sparse solver has become the bottleneck of SPICE simulators. There has been few work on GPU-based sparse solver because of the high data-dependency. The strong data-dependency determines that Parallel sparse LU factorization runs efficiently on shared-memory computing devices. But the number of CPU cores sharing the same memory is often limited. The state of the art Graphic Processing Units (GPU) naturally have numerous cores sharing the device memory, and provide a possible solution to the problem. In this paper, we propose a GPU-based sparse LU solver for Circuit simulation. We optimize the work partitioning, the number of active thread groups, and the memory access pattern, based on GPU architecture. On matrices whose factorization involves many floating-point operations, our GPU-based sparse LU factorization achieves 7.90× speedup over 1-core CPU and 1.49× speedup over 8-core CPU. We also analyze the scalability of Parallel sparse LU factorization and investigate the specifications on CPUs and GPUs that most influence the performance.
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an adaptive lu factorization algorithm for Parallel Circuit simulation
Asia and South Pacific Design Automation Conference, 2012Co-Authors: Xiaoming Chen, Yu Wang, Huazhong YangAbstract:Sparse matrix solver has become the bottleneck in SPICE simulator. It is difficult to Parallelize the solver because of the high data-dependency during the numerical LU factorization. This paper proposes a Parallel LU factorization (with partial pivoting) algorithm on shared-memory computers with multi-core CPUs, to accelerate Circuit simulation. Since not every matrix is suitable for Parallel algorithm, a predictive method is proposed to decide whether a matrix should use Parallel or sequential algorithm. The experimental results on 35 Circuit matrices reveal that the developed algorithm achieves speedups of 2.11×∼8.38× (on geometric-average), compared with KLU, with 1∼8 threads, on the matrices which are suitable for Parallel algorithm. Our solver can be downloaded from http://nicslu.weebly.com.
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DAC - Sparse LU factorization for Parallel Circuit simulation on GPU
Proceedings of the 49th Annual Design Automation Conference on - DAC '12, 2012Co-Authors: Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, Huazhong YangAbstract:Sparse solver has become the bottleneck of SPICE simulators. There has been few work on GPU-based sparse solver because of the high data-dependency. The strong data-dependency determines that Parallel sparse LU factorization runs efficiently on shared-memory computing devices. But the number of CPU cores sharing the same memory is often limited. The state of the art Graphic Processing Units (GPU) naturally have numerous cores sharing the device memory, and provide a possible solution to the problem. In this paper, we propose a GPU-based sparse LU solver for Circuit simulation. We optimize the work partitioning, the number of active thread groups, and the memory access pattern, based on GPU architecture. On matrices whose factorization involves many floating-point operations, our GPU-based sparse LU factorization achieves 7.90× speedup over 1-core CPU and 1.49× speedup over 8-core CPU. We also analyze the scalability of Parallel sparse LU factorization and investigate the specifications on CPUs and GPUs that most influence the performance.
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ASP-DAC - An adaptive LU factorization algorithm for Parallel Circuit simulation
17th Asia and South Pacific Design Automation Conference, 2012Co-Authors: Xiaoming Chen, Yu Wang, Huazhong YangAbstract:Sparse matrix solver has become the bottleneck in SPICE simulator. It is difficult to Parallelize the solver because of the high data-dependency during the numerical LU factorization. This paper proposes a Parallel LU factorization (with partial pivoting) algorithm on shared-memory computers with multi-core CPUs, to accelerate Circuit simulation. Since not every matrix is suitable for Parallel algorithm, a predictive method is proposed to decide whether a matrix should use Parallel or sequential algorithm. The experimental results on 35 Circuit matrices reveal that the developed algorithm achieves speedups of 2.11×∼8.38× (on geometric-average), compared with KLU, with 1∼8 threads, on the matrices which are suitable for Parallel algorithm. Our solver can be downloaded from http://nicslu.weebly.com.
