The Experts below are selected from a list of 315 Experts worldwide ranked by ideXlab platform

Pavan Kumar Hanumolu - One of the best experts on this subject based on the ideXlab platform.

  • analysis and design techniques for supply noise mitigation in Phase Locked Loops
    IEEE Transactions on Circuits and Systems I-regular Papers, 2010
    Co-Authors: Abhijith Arakali, Srikanth Gondi, Pavan Kumar Hanumolu
    Abstract:

    Supply noise affects the jitter performance of ring oscillator-based Phase-Locked Loops (PLLs) significantly. While the focus of much of the prior art is on supply noise in oscillators, this paper illustrates that supply noise in other building blocks also contribute significantly to PLL output jitter. Analytical expressions for supply-noise sensitivities are derived for each of the circuit blocks used in the PLL and insight into the mechanism through which supply noise appears at the PLL output is provided. Efficient supply-regulation schemes that combine a split-tuned PLL architecture with an optimized low-dropout regulator to achieve better than -22 dB of worst case supply-noise sensitivity for the whole PLL are presented. Fabricated in a 0.18 μm digital CMOS process, the prototype PLL occupies an area of 0.18 μm and operates from a 1.8 V supply. At 1.5 GHz, the total power consumption is 3.3 mW, of which 0.54 mW is consumed in the regulators. The measured output peak-to-peak jitter is 33 ps and 41 ps with no supply noise and with a 100-mV amplitude supply noise tone injected at the worst case noise frequency, respectively.

  • Analysis of charge-pump Phase-Locked Loops
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2004
    Co-Authors: Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram, Un-ku Moon
    Abstract:

    In this paper, we present an exact analysis for third-order charge-pump Phase-Locked Loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the loop parameters and the reference frequency on the loop Phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.

Salvatore Levantino - One of the best experts on this subject based on the ideXlab platform.

  • analysis and design of low jitter digital bang bang Phase Locked Loops
    IEEE Transactions on Circuits and Systems, 2014
    Co-Authors: Giovanni Marucci, Salvatore Levantino, Paolo Maffezzoni, Carlo Samori
    Abstract:

    Digital Phase-Locked Loops based on bang-bang Phase detectors are attractive candidates for low-jitter clock-frequency multiplication. Unfortunately, the coarse quantization of Phase error makes these systems prone to the generation of limit cycles appearing as unwanted spurs in the spectrum. The random noise contributed by building blocks and acting as dithering signal can eliminate those spurs. The quantitative analysis of those phenomena becomes more involved when a DCO with relaxed intrinsic resolution, such as a ΔΣ-DCO is employed, and when practical spectra of random noise sources are considered. In this work, the expression of jitter is calculated in closed-form taking into account the quantization, introduced by both Phase detector and DCO, and the Phase noise of DCO, with both 1/f 2 and 1/f 3 components. Combining these results, a closed-form expression of the total output jitter as a function of loop parameters and noise sources is developed which suggests a minimum-jitter design strategy. The proposed analysis and optimization are validated both numerically and experimentally on a 320-MHz digital bang-bang PLL fabricated in a 65-nm CMOS process.

  • Analysis of VCO Phase noise in charge-pump Phase-Locked Loops
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2012
    Co-Authors: Paolo Maffezzoni, Salvatore Levantino
    Abstract:

    This paper presents a Phase noise analysis of charge-pump Phase-Locked-Loops. Fundamental results from the theory of discrete-time systems are employed to derive closed-form expressions of noise transfer functions and design guidelines. The proposed expressions allows predicting the PLL in-band noise and spurs induced by VCO internal white and flicker noise sources and by external interferences coupled to VCO most sensitive nodes. To verify the correctness of the presented theoretical results, a simulation method is developed, which takes into account the time-varying nonlinear characteristics of the VCO and which is much more efficient than transistor-level noise simulations.

  • Folding of Phase noise spectra in charge-pump Phase-Locked Loops induced by frequency division
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2010
    Co-Authors: Salvatore Levantino, Luca Collamati, Carlo Samori, Andrea L. Lacaita
    Abstract:

    In charge-pump Phase-Locked Loops (CP-PLLs), the reference signal samples the Phase delay between reference and feedback signals. When a frequency divider is present in the loop, the spectrum folding of the voltage-controlled oscillator Phase noise caused by the inherent subsampling operation adds a relevant contribution to the in-band output noise. This brief elaborates the discrete-time linear model of PLLs to take into account spectrum folding and provides a simple equation for the estimation of the output noise. The closed-form expressions are validated on the basis of behavioral simulations of a third-order CP-PLL.

  • Quantization Effects in All-Digital Phase-Locked Loops
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2007
    Co-Authors: Paolo Madoglio, Salvatore Levantino, Carlo Samori, Marco Zanuso, Andrea L. Lacaita
    Abstract:

    This brief analyzes the impact of the quantization noise sources in all-digital Phase-Locked Loops (ADPLLs), recently employed as frequency synthesizers. In general, the in-band Phase noise is not only caused by the Phase quantization of the time-to-digital converter, but also by the frequency quantization of the digitally controlled oscillator (DCO). The delta-sigma modulator placed at the DCO input refines the frequency quantization and adds another source of in-band PLL noise. Interestingly, the higher the modulator order, the higher this source of in-band Phase noise. A method for the estimation of all the quantization noise contributors is provided, which is proven by mixed-mode simulations.

A. Demir - One of the best experts on this subject based on the ideXlab platform.

  • Computing Timing Jitter From Phase Noise Spectra for Oscillators and Phase-Locked Loops With White and$1/f$Noise
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2006
    Co-Authors: A. Demir
    Abstract:

    Phase noise and timing jitter in oscillators and Phase-Locked Loops (PLLs) are of major concern in wireless and optical communications. In this paper, a unified analysis of the relationships between time-domain jitter and various spectral characterizations of Phase noise is first presented. Several notions of Phase noise spectra are considered, in particular, the power-spectral density (PSD) of the excess Phase noise, the PSD of the signal generated by a noisy oscillator/PLL, and the so-called single-sideband (SSB) Phase noise spectrum. We investigate the origins of these Phase noise spectra and discuss their mathematical soundness. A simple equation relating the variance of timing jitter to the Phase noise spectrum is derived and its mathematical validity is analyzed. Then, practical results on computing jitter from spectral Phase noise characteristics for oscillators and PLLs with both white (thermal, shot) and 1/f noise are presented. We are able to obtain analytical timing jitter results for free-running oscillators and first-order PLLs. A numerical procedure is used for higher order PLLs. The Phase noise spectrum needed for computing jitter may be obtained from analytical Phase noise models, oscillator or PLL noise analysis in a circuit simulator, or from actual measurements

Lennart Harnefors - One of the best experts on this subject based on the ideXlab platform.

  • small signal modeling of three Phase synchronous reference frame Phase Locked Loops
    IEEE Transactions on Power Electronics, 2018
    Co-Authors: Florian Hans, Walter Schumacher, Lennart Harnefors
    Abstract:

    Synchronous reference frame (SRF) Phase-Locked Loops (PLLs) represent a commonly used technique for grid synchronization in distributed generation (DG) systems. Since PLLs affect transient dynamics, they are a crucial component for stability studies. In this letter, it is shown that a commonly used small-signal SRF-PLL model can be used for stability analysis in some preconditioned scenarios with a single grid-connected DG unit, but does necessarily require perturbation quantities that are offset free. Otherwise, an incorrect usage may result in unacceptable errors. To overcome this restriction, an improved small-signal PLL model is proposed, which enables to analyze the effects of grid frequency and Phase angle changes as well as variations of the input voltage magnitude. Finally, the model accuracy is validated by means of computer simulations.

Larry Pileggi - One of the best experts on this subject based on the ideXlab platform.

  • formal verification of Phase Locked Loops using reachability analysis and continuization
    Communications of The ACM, 2013
    Co-Authors: Matthias Althoff, Akshay Rajhans, Bruce H Krogh, Soner Yaldiz, Larry Pileggi
    Abstract:

    We present a scalable and formal technique to verify locking time and stability for charge-pump Phase-Locked Loops (PLLs). In contrast to the traditional simulation approach that only validates the PLL at a given operation condition, our proposed technique formally verified the PLL at all possible operation conditions. The dynamics of the PLL is described by a hybrid automaton, which incorporates the differential equations of the analog circuit elements as well as the switching logic of the digital circuit elements. Existing methods for computing reachable sets for hybrid automata cannot be used to verify the PLL model due to the large number of cycles required for locking. We develop a new method for computing effective overapproximations of the sets of states reached on each cycle by using uncertain parameters in a discrete-time model to represent the range of possible switching times, a technique we call continuization. Using this new method for reachability analysis, it is possible to verify locking specifications for a charge-pump PLL design for all possible initial states and parameter values in time comparable to the time required for a few simulation runs of the same behavioral model.

  • formal verification of Phase Locked Loops using reachability analysis and continuization
    International Conference on Computer Aided Design, 2011
    Co-Authors: Matthias Althoff, Akshay Rajhans, Bruce H Krogh, Soner Yaldiz, Larry Pileggi
    Abstract:

    We present an approach for verifying locking of charge-pump Phase-Locked Loops by performing reachability analysis on a behavioral model of the circuit. Bounded uncertain parameters in the behavioral model make it possible to represent all possible behaviors of more detailed models. The dynamics of the behavioral model is hybrid (i.e., discrete and continuous) due to the switching of charge pumps that drive the analog control circuits. A unique feature of Phase-Locked Loops compared to most other hybrid systems is that they require thousands of switchings in the continuous dynamics to converge sufficiently close to a limit cycle. This makes reachability analysis a challenging task since switches in the dynamics are expensive to compute and result in conservative overapproximations. We solve this problem by overapproximating the effects of the switching conditions with uncertain parameters in linear continuous models, a method we call continuization. Using efficient reachability algorithms for discrete-time linear systems, locking is verified over the complete range of possible initial states of a charge-pump PLL designed in 32nm CMOS SOI technology in comparable time required for Monte Carlo simulations of the same behavioral model.