The Experts below are selected from a list of 39810 Experts worldwide ranked by ideXlab platform
K. Mourgues F. Raoult T. Mohammed-brahim K. Kis-sion - One of the best experts on this subject based on the ideXlab platform.
-
Thin film transistors fabricated by in-situ doped unhydrogenated Polysilicon films obtained by solid phase crystallization
Semiconductor Science and Technology, 2001Co-Authors: Laurent Pichon, K. Mourgues F. Raoult T. Mohammed-brahim K. Kis-sionAbstract:High mobility low temperature (≤ 600°C) unhydrogenated in-situ doped Polysilicon thin film transistors are made. Polysilicon layers are grown by a LPCVD technique and crystallized in vacuum by a thermal annealing. Source and drain regions are in-situ doped. Gate insulator is made of an APCVD silicon dioxide. Hydrogen passivation is not performed on the transistors. One type of transistors is made of two Polysilicon layers, the other one is constituted of a single Polysilicon layer. The electrical properties are better for transistors made of single Polysilicon layer: a low threshold voltage (1.2 V), a subthreshold slope S = 0.7 V/dec, a high field effect mobility (≈ 100 cm2/Vs) and a On/Off state current ratio higher than 107 for a drain voltage Vds = 1 V. At low drain voltage, for both transistors, the Off state current results from a pure thermal emission of trapped carriers. However, at high drain voltage, the electrical behavior is different: in the case of single Polysilicon TFTs, the current obeys the field-assisted (Poole-Frenkel) thermal emission model of trapped carriers while for TFTs made of two Polysilicon layers, the higher Off state current results from a field-enhanced thermal emission.
Laurent Pichon - One of the best experts on this subject based on the ideXlab platform.
-
Fully compatible CMOS technology Polysilicon nanowires for integrated gas sensing applications
2011Co-Authors: Laurent Pichon, Fouad Demami, Régis Rogel, Anne-claire Salaün, Emmanuel Jacques, Gertrude Godem-wengaAbstract:Polysilicon nanowires are synthesized using a low cost classical top-down fabrication technique commonly used in microelectronic industry: the sidewall spacer formation technique. Polysilicon layer is deposited by Low Pressure Chemical Vapour Deposition technique on SiO2 wall patterned by conventional UV lithography technique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of nanometric size sidewall spacers with 50nm and 100nm curvature radius used as Polysilicon nanowires]. N- and P-type in-situ doping control of these Polysilicon nanowires over a large range, from 2.1016 at.cm-3 to 2.1020 at.cm-3, is demonstrated. These nanowires are integrated into the fabrication of electrical devices (resistors, transistors) and electrical properties are studied in function of in-situ doping levels. I(T) measurements show that Polysilicon nanowires dark conductivity is thermally activated following the Mott or Seto's theories related to the nanowires size dependent structural quality. Charged gas species (ammonia) sensitivity of these nanowires has also been studied. In addition, feasibility of N- and P-channel Polysilicon nanowires transistors is demonstrated. Such results show the full compatibility of the nanospacer Polysilicon nanowires technology with the existing silicon CMOS technology using nanowires as potential sensitive units for integrated gas sensors applications.
-
Electrical properties of Polysilicon nanowires for devices applications
physica status solidi (c), 2011Co-Authors: Fouad Demami, Régis Rogel, Anne-claire Salaün, Laurent PichonAbstract:Polysilicon nanowires are synthesized using the well known and low cost technique commonly used in microelectronic industry: the sidewall spacer formation technique. Polysilicon layer is de-posited by Low Pressure Chemical Vapour Deposition technique on SiO2 wall patterned by conventional UV lithography tech-nique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of nanometric size side-wall spacers with a curvature radius as low as 100nm used as Polysilicon nanowires. These Polysilicon nanowires are first in-tegrated into the fabrication of electrical devices as resistors and electrical properties are studied in function of in situ phosphorus doping levels. I(T) measurements show that Polysilicon nanowires dark conductivity is thermally activated according to the Seto's theory. In addition, field effect transistors made with such Polysilicon nanowires used as channel region highlight promising field effect behaviour.
-
Electrical properties of Polysilicon nanowires for device applications
Physica Status Solidi (c), 2010Co-Authors: Fouad Demami, Régis Rogel, Anne-claire Salaün, Laurent PichonAbstract:Polysilicon nanowires are synthesized using the well known and low cost technique commonly used in microelectronic industry: the sidewall spacer formation technique. Polysilicon layer is deposited by Low Pressure Chemical Vapour Deposition technique on SiO2 wall patterned by conventional UV lithography technique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of nanometric size sidewall spacers with a curvature radius as low as 100 nm used as Polysilicon nanowires. These Polysilicon nanowires are first integrated into the fabrication of electrical devices as resistors and electrical properties are studied in function of in situ phosphorus doping levels. I(T) measurements show that Polysilicon nanowires dark conductivity is thermally activated according to the Seto's theory. In addition, field effect transistors made with such Polysilicon nanowires used as channel region highlight promising field effect behaviour. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
-
Electrical properties of Polysilicon nanowires for devices applications
2010Co-Authors: Fouad Demami, Régis Rogel, Anne-claire Salaün, Laurent PichonAbstract:In this work, we processed Polysilicon nanowires using the well known and low cost technique commonly used in microelectronic industry: the sidewall spacer formation technique. In our process, a Polysilicon layer is deposited by LPCVD (Low Pressure Chemical Vapour Deposition) technique on SiO2 wall patterned by conventional UV lithography technique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of nanometric size sidewall spacers with a curvature radius below 100nm. N-type in-situ doping process of such Polysilicon nanowires is ensured by incorporation of phosphine during deposition of Polysilicon. Polysilicon nanowires were integrated into the fabrication of electrical devices as resistors. Effect of in situ phosphorus doping was investigated, doping levels varying from 1016 to 2.1020 at/cm3. Polysilicon nanowires dark conductivity versus temperature was measured leading to the determination of conductivity activation energy values that are compared to those obtained for corresponding Polysilicon layers. In addition, Thin Film Transistors were also fabricated using Polysilicon nanowires as channel region highlighting a very promising field effect behaviour.
-
Thin film transistors fabricated by in-situ doped unhydrogenated Polysilicon films obtained by solid phase crystallization
Semiconductor Science and Technology, 2001Co-Authors: Laurent Pichon, K. Mourgues F. Raoult T. Mohammed-brahim K. Kis-sionAbstract:High mobility low temperature (≤ 600°C) unhydrogenated in-situ doped Polysilicon thin film transistors are made. Polysilicon layers are grown by a LPCVD technique and crystallized in vacuum by a thermal annealing. Source and drain regions are in-situ doped. Gate insulator is made of an APCVD silicon dioxide. Hydrogen passivation is not performed on the transistors. One type of transistors is made of two Polysilicon layers, the other one is constituted of a single Polysilicon layer. The electrical properties are better for transistors made of single Polysilicon layer: a low threshold voltage (1.2 V), a subthreshold slope S = 0.7 V/dec, a high field effect mobility (≈ 100 cm2/Vs) and a On/Off state current ratio higher than 107 for a drain voltage Vds = 1 V. At low drain voltage, for both transistors, the Off state current results from a pure thermal emission of trapped carriers. However, at high drain voltage, the electrical behavior is different: in the case of single Polysilicon TFTs, the current obeys the field-assisted (Poole-Frenkel) thermal emission model of trapped carriers while for TFTs made of two Polysilicon layers, the higher Off state current results from a field-enhanced thermal emission.
A Asenov - One of the best experts on this subject based on the ideXlab platform.
-
quantitative evaluation of statistical variability sources in a 45 nm technological node lp n mosfet
IEEE Electron Device Letters, 2008Co-Authors: A Cathignol, B Cheng, D Chanemougame, A R Brown, K Rochereau, G Ghibaudo, A AsenovAbstract:A quantitative evaluation of the contributions of different sources of statistical variability, including the contribution from the Polysilicon gate, is provided for a low-power bulk N-MOSFET corresponding to the 45-nm technology generation. This is based on a joint study including both experimental measurements and ldquoatomisticrdquo simulations on the same fully calibrated device. The position of the Fermi-level pinning in the Polysilicon bandgap that takes place along grain boundaries was evaluated, and Polysilicon-gate-granularity contribution was compared to the contributions of other variability sources. The simulation results indicate that random discrete dopants are still the dominant intrinsic source of statistical variability, while the role of Polysilicon-gate granularity is highly dependent on Fermi-level pinning position and, consequently, on the structure of the Polysilicon-gate material and its deposition and annealing conditions.
Sejin Kwon - One of the best experts on this subject based on the ideXlab platform.
-
Effect of high-temperature glass frit bonding process on performance of Polysilicon strain gauges
Micro & Nano Letters, 2012Co-Authors: Sejin KwonAbstract:This Letter presents the effect of high-temperature glass frit bonding conditions on the resistivity coefficient of gauge factor (RCGF), resistivity and gauge factor of Polysilicon strain gauges. In previous works, the authors proposed the use of thin Polysilicon strain gauges that were bonded onto metal structures with an inorganic glass frit adhesive. However, this glass frit bonding process was carried out at a high temperature, which could cause performance changes of the Polysilicon strain gauges in terms of their RCGF, resistivity and gauge factor. To investigate the effect of the glass frit bonding process, the RCGF, resistivity and gauge factor of the Polysilicon strain gauge before and after heat treatment by the conventional Al annealing condition and the glass frit bonding condition were compared and evaluated. In the results, large resistivity and gauge factor deviations in the Polysilicon strain gauges that were not heat treated were observed. In spite of these large deviations, a linear relationship between the resistivity and the gauge factor was observed. After the Polysilicon strain gauges were heat treated by the conventional Al annealing condition and the glass frit bonding condition, the deviations in the values of the resistivity and gauge factor became more uniform than those seen in the strain gauges that were not heat treated. The RCGFs of the Polysilicon strain gauges heat treated with the Al annealing condition and the glass frit bonding condition coincided with that of the gauge that was not heat treated.
-
resistivity dependence of gauge factor of Polysilicon strain gauge
Micro & Nano Letters, 2010Co-Authors: Sejin KwonAbstract:A method to estimate the gauge factor of a Polysilicon strain gauge at the wafer level is proposed. It is difficult to measure the gauge factor of a Polysilicon strain gauge formed on the silicon diaphragm of a mechanical transducer because the Polysilicon strain gauge is integrated into the diaphragm. The authors fabricated Polysilicon strain gauges of various shapes and implanted with various concentrations of boron, and measured the gauge factor of each strain gauge. In the experimental results, the gauge factors are calculated by multiplying the resistivity coefficient of gauge factor (RCGF) determined by the boron concentration and resistivity of the Polysilicon strain gauge. The authors also determined the RCGF of the Polysilicon strain gauges implanted with boron concentrations of 1.0×1019, 1.5×1019 and 1.0×1020 cm−3.
Khalil Najafi - One of the best experts on this subject based on the ideXlab platform.
-
High aspect-ratio Polysilicon micromachining technology
Sensors and Actuators A: Physical, 2000Co-Authors: Farrokh Ayazi, Khalil NajafiAbstract:This paper presents a single wafer, all-silicon, high aspect-ratio multi-layer Polysilicon micromachining technology that combines deep dry etching of silicon with conventional surface micromachining to realize tens to hundreds of microns thick, high aspect-ratio, electrically isolated Polysilicon structures with sub-micron air-gaps. Vertical Polysilicon sense electrodes as tall as the main body Polysilicon structure can be realized in this technology. A 70-μm-tall, 2.5-μm-wide Polysilicon vibrating ring gyroscope with 1.2 μm capacitive air-gaps and electrodes as tall as the ring structure has been fabricated using this technology. Vertical Polysilicon beams that are 220 μm tall with a 100:1 aspect-ratio have been also fabricated. The all-silicon feature of such a technology improves long term stability and temperature sensitivity, while fabrication of large area, vertical pick-off electrodes with sub-micron gap spacing will increase the sensitivity of MEMS devices by orders of magnitude. This technology is also capable of simultaneously producing electrically isolated 2-D (planar) and 3-D (vertical) Polysilicon structures on the same silicon substrate.
