The Experts below are selected from a list of 96 Experts worldwide ranked by ideXlab platform

Erik Larsson - One of the best experts on this subject based on the ideXlab platform.

  • ITC - Access time minimization in IEEE 1687 networks
    2015 IEEE International Test Conference (ITC), 2015
    Co-Authors: Rene Krenz-baath, Farrokh Ghani Zadegan, Erik Larsson
    Abstract:

    IEEE 1687 enables flexible access to the embedded (on-chip) instruments that are needed for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and in-field test. At any of these scenarios, the instruments are accessed differently, and at a given scenario the instruments are accessed differently over time. It means the IEEE 1687 network needs to be frequently reconfigured from accessing one set of instruments to accessing a different set of instruments. Due to the need of frequent reconfiguration of the IEEE 1687 network it is important to (1) minimize the runtime for the algorithm finding the new reconfiguration, and (2) generate scan vectors with minimized access time. In this paper we model the reconfiguration problem using Boolean Satisfiability Problem (SAT). Compared to previous works we show significant reduction in run-time and we ensure minimal access time for the generated scan vectors.

  • ATS - Design, Verification, and Application of IEEE 1687
    2014 IEEE 23rd Asian Test Symposium, 2014
    Co-Authors: Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-baath
    Abstract:

    IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time.

  • ITC - Robustness of TAP-based scan networks
    2014 International Test Conference, 2014
    Co-Authors: Farrokh Ghani Zadegan, Gunnar Carlsson, Erik Larsson
    Abstract:

    It is common to embed instruments when developing integrated circuits (ICs). These instruments are accessed at post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and operator-driven in-field test. At any of these scenarios, it is of interest to access some but not all of the instruments. IEEE 1149.1-2013 and IEEE 1687 propose Test Access Port based (TAP-based) mechanisms to design flexible scan networks such that any combination of instruments can be accessed from outside of the IC. Previous works optimize TAP-based scan networks for one scenario with a known number of accesses. However, at design time, it is difficult to foresee all needed scenarios and the exact number of accesses to instruments. Moreover, the number of accesses might change due to late design changes, addition/exclusion of tests, and changes of constraints. In this paper, we analyze and compare seven IEEE 1687 compatible network design approaches in terms of instrument access time, hardware overhead, and robustness. Given the similarities between IEEE 1149.1-2013 and IEEE 1687, the conclusions are also applicable to IEEE 1149.1-2013 networks.

Kazumi Hatayama - One of the best experts on this subject based on the ideXlab platform.

  • VTS - Innovative practices on test in Japan
    2018 IEEE 36th VLSI Test Symposium (VTS), 2018
    Co-Authors: Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama
    Abstract:

    The IP session highlights three innovative practices in Asia, which include low cost testing of analog front-end circuits, evaluation of complex analog filter and power reduction of power-on self-test for automotive MCU.

Rene Krenz-baath - One of the best experts on this subject based on the ideXlab platform.

  • ITC - Access time minimization in IEEE 1687 networks
    2015 IEEE International Test Conference (ITC), 2015
    Co-Authors: Rene Krenz-baath, Farrokh Ghani Zadegan, Erik Larsson
    Abstract:

    IEEE 1687 enables flexible access to the embedded (on-chip) instruments that are needed for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board bring-up, printed circuit board assembly manufacturing test, power-on self-test, and in-field test. At any of these scenarios, the instruments are accessed differently, and at a given scenario the instruments are accessed differently over time. It means the IEEE 1687 network needs to be frequently reconfigured from accessing one set of instruments to accessing a different set of instruments. Due to the need of frequent reconfiguration of the IEEE 1687 network it is important to (1) minimize the runtime for the algorithm finding the new reconfiguration, and (2) generate scan vectors with minimized access time. In this paper we model the reconfiguration problem using Boolean Satisfiability Problem (SAT). Compared to previous works we show significant reduction in run-time and we ensure minimal access time for the generated scan vectors.

  • ATS - Design, Verification, and Application of IEEE 1687
    2014 IEEE 23rd Asian Test Symposium, 2014
    Co-Authors: Farrokh Ghani Zadegan, Erik Larsson, Artur Jutman, Sergei Devadze, Rene Krenz-baath
    Abstract:

    IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the increasing number of embedded instruments in today's integrated circuits. These instruments enable efficient post-silicon validation, debugging, wafer sort, package test, burn-in, bring-up and manufacturing test of printed circuit board assemblies, power-on self-test, and in-field test. Current paper presents an overview of challenges as well as selected examples in the following topics around IEEE 1687 networks: (1) design to efficiently access the embedded instruments, (2) verification to ensure correctness, and (3) fault management at functions performed in-field through the product's life time.

Jun Matsushima - One of the best experts on this subject based on the ideXlab platform.

  • VTS - Innovative practices on test in Japan
    2018 IEEE 36th VLSI Test Symposium (VTS), 2018
    Co-Authors: Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama
    Abstract:

    The IP session highlights three innovative practices in Asia, which include low cost testing of analog front-end circuits, evaluation of complex analog filter and power reduction of power-on self-test for automotive MCU.

  • Automotive Functional Safety Assurance by POST with Sequential Observation
    IEEE Design & Test, 2018
    Co-Authors: Senling Wang, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima
    Abstract:

    power-on self-test is an efficient means for covering safety-critical faults in automotive systems. This paper presents a multicycle logic BIST technique that avoids fault masking after multiple cycles by sequential observation using a new scan cell structure. —Hans-Joachim Wunderlich, Universitat Stuttgart

  • ATS - Capture-Pattern-Control to Address the Fault Detection Degradation Problem of Multi-cycle Test in Logic BIST
    2018 IEEE 27th Asian Test Symposium (ATS), 2018
    Co-Authors: Senling Wang, Yoichi Maeda, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Tomoki Aono, Jun Matsushima
    Abstract:

    Multi-cycle Test applies more than one capture cycles during the capture operation which is a promising way to reduce the test volume of Logic-BIST (Logic Built-in self-test) based POST (power-on self-test) for achieving high fault coverage. However, the randomness loss of the capture patterns due to the large number of capture cycles obstructs the further improvement of fault coverage and pattern reduction. In this paper, we propose a novel approach to control the capture patterns by modifying the captured values of scan Flip-Flops (FFs) during capture operation to enhance the test quality of the capture patterns. In the approach, we insert FF-Control circuits between the scan FFs and the combinational circuit to improve the randomness of the capture patterns by loading toggle vectors/pseudo-random vectors. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction for Logic-BIST.

Koji Asami - One of the best experts on this subject based on the ideXlab platform.

  • VTS - Innovative practices on test in Japan
    2018 IEEE 36th VLSI Test Symposium (VTS), 2018
    Co-Authors: Koji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama
    Abstract:

    The IP session highlights three innovative practices in Asia, which include low cost testing of analog front-end circuits, evaluation of complex analog filter and power reduction of power-on self-test for automotive MCU.