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D.m.h. Walker - One of the best experts on this subject based on the ideXlab platform.

  • Power Supply Noise control in pseudo functional test
    VLSI Test Symposium, 2013
    Co-Authors: Tengteng Zhang, D.m.h. Walker
    Abstract:

    Pseudo functional K Longest Path Per Gate (KLPG) test (PKLPG) is proposed to generate delay tests that test the longest paths while having Power Supply Noise similar to that seen during normal functional operation. Our experimental results show that PKLPG is more vulnerable to under-testing than traditional two-cycle transition fault test. In this work, a simulation-based X'Filling method, Bit-Flip, is proposed to maximize the Power Supply Noise during PKLPG test. Given a set of partially-specified scan patterns, random filling is done and then an iterative procedure is invoked to flip some of the filled bits, to increase the effective weighted switching activity (WSA). Experimental results on both compacted and uncompacted test patterns are presented. The results demonstrate that our method can significantly increase effective WSA while limiting the fill rate.

  • VTS - Power Supply Noise control in pseudo functional test
    2013 IEEE 31st VLSI Test Symposium (VTS), 2013
    Co-Authors: Tengteng Zhang, D.m.h. Walker
    Abstract:

    Pseudo functional K Longest Path Per Gate (KLPG) test (PKLPG) is proposed to generate delay tests that test the longest paths while having Power Supply Noise similar to that seen during normal functional operation. Our experimental results show that PKLPG is more vulnerable to under-testing than traditional two-cycle transition fault test. In this work, a simulation-based X'Filling method, Bit-Flip, is proposed to maximize the Power Supply Noise during PKLPG test. Given a set of partially-specified scan patterns, random filling is done and then an iterative procedure is invoked to flip some of the filled bits, to increase the effective weighted switching activity (WSA). Experimental results on both compacted and uncompacted test patterns are presented. The results demonstrate that our method can significantly increase effective WSA while limiting the fill rate.

  • MTV - Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits
    Seventh International Workshop on Microprocessor Test and Verification (MTV'06), 2006
    Co-Authors: Hyun Sung Kim, D.m.h. Walker
    Abstract:

    As semiconductor technology is scaled and voltage level is reduced, the impact of Power Supply variation has become very significant in predicting the realistic worst-case delays in integrated circuits. The analysis of Power Supply Noise is inevitable since there is a high correlation between delay and Supply voltage. Supply Noise analysis has often used a vector-based STA approach. However, vector-based approaches are very expensive, particularly during the design phase. In this work, two novel vectorless approaches are described such that circuit delay increases due to Power Supply Noise can be efficiently estimated. Experimental results on ISCAS89 circuits show not only the accuracy of our approaches, but also the indispensability of considering care-bits, which sensitize the longest paths during the Power Supply Noise analysis.

  • a vector based approach for Power Supply Noise analysis in test compaction
    International Test Conference, 2005
    Co-Authors: Jing Wang, Wangqi Qiu, Ziding Yue, Weiping Shi, D.m.h. Walker
    Abstract:

    Excessive Power Supply Noise can lead to overkill during delay test. A static test vector compaction solution is described to prevent such overkill. Low-cost Power Supply Noise models are developed and used in compaction. An error analysis of these models is given. This paper improves on prior work in terms of models and algorithm to increase accuracy and performance. Experimental results are given on ISCAS89 circuits

  • VTS - Static compaction of delay tests considering Power Supply Noise
    23rd IEEE VLSI Test Symposium (VTS'05), 1
    Co-Authors: Jing Wang, Wangqi Qiu, S. Fancler, D.m.h. Walker, Ziding Yue, Weiping Shi
    Abstract:

    Excessive Power Supply Noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A Power Supply Noise estimation tool has been built and integrated into the compaction process. Compaction results for KLPG delay tests for ISCAS89 circuits under different Power grid environments are presented.

Kwang-ting Cheng - One of the best experts on this subject based on the ideXlab platform.

  • Vector generation for Power Supply Noise estimation and verification of deep submicron designs
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2001
    Co-Authors: Yi-min Jiang, Kwang-ting Cheng
    Abstract:

    This paper presents new techniques for generating a small set of patterns for Power network simulation to estimate the maximum Power Supply Noise of the chip, as well as to identify cells/blocks for which the Power Supply Noise at their V/sub dd/ ports exceeds a specified threshold. We first present an efficient, cell-level simulator for estimating Power Supply Noise of any given vectors. Based on this simulator, we then apply the genetic algorithm (GA) to derive a small set of patterns producing high Power Supply Noise. To identify critical nodes with Power Supply Noise exceeding a threshold, the multiobjective GA is adapted for pattern generation. To achieve high coverage of such critical nodes, we model the search criteria as the maximum weighted matching of a bipartite graph, and guide the search direction according to the matching results. The derived patterns will be simulated on a Power network simulator to obtain a lower bound of the maximum Power Supply Noise and to identify the critical nodes. Experimental results on public benchmark circuits, as well as some industrial designs, are presented to demonstrate the efficiency and effectiveness of the proposed approaches.

  • path selection and pattern generation for dynamic timing analysis considering Power Supply Noise effects
    International Conference on Computer Aided Design, 2000
    Co-Authors: Jingjia Liou, Yi-min Jiang, Angela Krstic, Kwang-ting Cheng
    Abstract:

    Noise effects such as Power Supply and crosstalk can significantly affect the performance of deep submicron designs. These delay effects are highly input pattern dependent. Existing path selection and timing analysis techniques cannot capture the effects of Noise on cell/interconnect delays. Therefore, the selected critical paths may not be the longest paths and predicted circuit performance might not reflect the worst-case circuit delay. In this paper, we propose a path selection technique that can consider Power Supply Noise effects on the propagation delays. Next, for the selected critical paths, we propose a pattern generation technique for dynamic timing analysis such that the patterns produce the worst-case Power Supply Noise effects on the delays of these paths. Our experimental results demonstrate the difference in estimated circuit performance for the case when Power Supply Noise effects are considered vs. when these effects are ignored. Thus, they validate the need for considering Power Supply Noise effects on delays during path selection and dynamic timing analysis.

  • estimation of maximum Power Supply Noise for deep sub micron designs
    International Symposium on Low Power Electronics and Design, 1998
    Co-Authors: Yi-min Jiang, Kwang-ting Cheng, Anchang Deng
    Abstract:

    We propose a new technique for generating a small set of patterns to estimate the maximum Power Supply Noise of deep sub-micron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking Power and ground pin characteristics, the Power net RC and other input characteristics as parameters. Based on the cells' current and voltage libraries, the Power Supply Noise of a 2-vector sequence can be estimated efficiently by a cell-level waveform simulator. We then apply the Genetic Algorithm based on the efficient waveform simulator to generate a small set of patterns producing high Power Supply Noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum Power Supply Noise.

  • ISLPED - Estimation of maximum Power Supply Noise for deep sub-micron designs
    Proceedings of the 1998 international symposium on Low power electronics and design - ISLPED '98, 1998
    Co-Authors: Yi-min Jiang, Kwang-ting Cheng, Anchang Deng
    Abstract:

    We propose a new technique for generating a small set of patterns to estimate the maximum Power Supply Noise of deep sub-micron designs. We first build the charge/discharge current and output voltage waveform libraries for each cell, taking Power and ground pin characteristics, the Power net RC and other input characteristics as parameters. Based on the cells' current and voltage libraries, the Power Supply Noise of a 2-vector sequence can be estimated efficiently by a cell-level waveform simulator. We then apply the Genetic Algorithm based on the efficient waveform simulator to generate a small set of patterns producing high Power Supply Noise. Finally, the results are validated by simulating the obtained patterns using a transistor level simulator. Our experimental results show that the patterns generated by our approach produce a tight lower bound on the maximum Power Supply Noise.

  • ISQED - Dynamic timing analysis considering Power Supply Noise effects
    Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525), 1
    Co-Authors: Yi-min Jiang, Angela Krstić, Kwang-ting Cheng
    Abstract:

    Power Supply Noise can significantly impact the performance of deep submicron designs. Existing timing analysis techniques cannot capture the effects of Power Supply Noise on the signal/cell delays. This is because these delay effects are highly input pattern dependent. Therefore, the predicted circuit performance might not reflect the worst-case circuit delay. In this paper, we propose a dynamic timing analysis technique that can take into account the impact of the Power Supply Noise on the signal/cell propagation delays. Our technique is based on considering the input patterns that produce the worst-case Power Supply Noise effects on the propagation delays of the longest true paths in the circuit. Our experimental results show that the circuit delay predicted by our dynamic timing analysis method is significantly longer than the delay predicted suing traditional timing analysis tools.

Weiping Shi - One of the best experts on this subject based on the ideXlab platform.

Mehrdad Nourani - One of the best experts on this subject based on the ideXlab platform.

  • Power Supply Noise in socs atpg estimation and control
    International Test Conference, 2005
    Co-Authors: Mehrdad Nourani, A Radhakrishnan
    Abstract:

    Noise on the Power-Supply lines has become a critical factor especially in low-voltage designs as excessive Noise may cause intermittent functional error and eventually system failure. Having a realistic picture of the worst case Noise throughout a chip is important as we can devise a remedy to alleviate the problem before it becomes too late. This paper provides a fast automatic pattern generation method to estimate the maximum simultaneous switching Noise for a non-embedded core. When the cores are integrated within a SoC, the combined Noise is far from a simple additive behavior. We offer a heuristic to estimate the Power-Supply Noise in core-based SoCs. This heuristic can be employed to minimize the number of Power-Supply lines/pins while keeping the Noise under control. The experiments using ISCAS'85 benchmarks verify that our Power-Supply Noise methodology is fairly fast and accurate and can be used for effective Power-Supply distribution

  • Pattern generation and estimation for Power Supply Noise analysis
    23rd IEEE VLSI Test Symposium (VTS'05), 2005
    Co-Authors: Mehrdad Nourani, N. Ahmed
    Abstract:

    This paper presents an automatic pattern generation methodology to stimulate the maximum Power Supply Noise in deep submicron CMOS circuits. Our ATPG-based approach first generates the required patterns to cover 0 /spl rarr/ 1 and 1 /spl rarr/ 0 transitions on each node of internal circuitry. Then, we apply a greedy heuristic to find the worst-case (maximum) instantaneous current and stimulate maximum switching activity inside the circuit. The quality of these patterns was verified by SPICE simulation. Experimental results show that the pattern pair generated by this approach produces a tight lower bound on the maximum Power Supply Noise.

  • VTS - Pattern generation and estimation for Power Supply Noise analysis
    23rd IEEE VLSI Test Symposium (VTS'05), 2005
    Co-Authors: Mehrdad Nourani, N. Ahmed
    Abstract:

    This paper presents an automatic pattern generation methodology to stimulate the maximum Power Supply Noise in deep submicron CMOS circuits. Our ATPG-based approach first generates the required patterns to cover 0 /spl rarr/ 1 and 1 /spl rarr/ 0 transitions on each node of internal circuitry. Then, we apply a greedy heuristic to find the worst-case (maximum) instantaneous current and stimulate maximum switching activity inside the circuit. The quality of these patterns was verified by SPICE simulation. Experimental results show that the pattern pair generated by this approach produces a tight lower bound on the maximum Power Supply Noise.

  • ITC - Power-Supply Noise in SoCs: ATPG, estimation and control
    IEEE International Conference on Test 2005., 1
    Co-Authors: Mehrdad Nourani, A Radhakrishnan
    Abstract:

    Noise on the Power-Supply lines has become a critical factor especially in low-voltage designs as excessive Noise may cause intermittent functional error and eventually system failure. Having a realistic picture of the worst case Noise throughout a chip is important as we can devise a remedy to alleviate the problem before it becomes too late. This paper provides a fast automatic pattern generation method to estimate the maximum simultaneous switching Noise for a non-embedded core. When the cores are integrated within a SoC, the combined Noise is far from a simple additive behavior. We offer a heuristic to estimate the Power-Supply Noise in core-based SoCs. This heuristic can be employed to minimize the number of Power-Supply lines/pins while keeping the Noise under control. The experiments using ISCAS'85 benchmarks verify that our Power-Supply Noise methodology is fairly fast and accurate and can be used for effective Power-Supply distribution

Jing Wang - One of the best experts on this subject based on the ideXlab platform.

  • Modeling Power Supply Noise in Delay Testing
    IEEE Design & Test of Computers, 2007
    Co-Authors: Jing Wang, A Majhi, B Kruseman, G Gronthoud, Luis Villagra, Paul Van De Wiel, Duncan M. Walker, Xiang Lu, S Eichenberger
    Abstract:

    Excessive Power Supply Noise during test can cause overkill. This article discusses two models for Supply Noise in delay testing and their application to test compaction. The proposed Noise models avoid complicated Power network analysis, making them much faster than existing Power Noise analysis tools. can cause performance degradation and

  • Power Supply Noise in delay testing
    International Test Conference, 2006
    Co-Authors: Jing Wang, D H Walker, A Majhi, B Kruseman, G Gronthoud, Luis Villagra, Paul Van De Wiel, S Eichenberger
    Abstract:

    Excessive Power Supply Noise can affect path delay and cause overkill during delay test. This paper presents low-cost Noise models for fast Power Supply Noise analysis and timing analysis considering Noise impact. Our prior work only considered array-bond chips. This work proposes a Noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The Power Supply Noise impact on delay must be taken into account when delay tests are applied.

  • ITC - Power Supply Noise in Delay Testing
    2006 IEEE International Test Conference, 2006
    Co-Authors: Jing Wang, D H Walker, A Majhi, B Kruseman, G Gronthoud, Luis Villagra, Paul Van De Wiel, S Eichenberger
    Abstract:

    Excessive Power Supply Noise can affect path delay and cause overkill during delay test. This paper presents low-cost Noise models for fast Power Supply Noise analysis and timing analysis considering Noise impact. Our prior work only considered array-bond chips. This work proposes a Noise analysis methodology that can be applied to wire-bond chips as well as array-bond chips. Experiments were performed on an industrial design. Silicon results show as much as a 15% delay variation due to different don't care fill approaches. The Power Supply Noise impact on delay must be taken into account when delay tests are applied.

  • a vector based approach for Power Supply Noise analysis in test compaction
    International Test Conference, 2005
    Co-Authors: Jing Wang, Wangqi Qiu, Ziding Yue, Weiping Shi, D.m.h. Walker
    Abstract:

    Excessive Power Supply Noise can lead to overkill during delay test. A static test vector compaction solution is described to prevent such overkill. Low-cost Power Supply Noise models are developed and used in compaction. An error analysis of these models is given. This paper improves on prior work in terms of models and algorithm to increase accuracy and performance. Experimental results are given on ISCAS89 circuits

  • VTS - Static compaction of delay tests considering Power Supply Noise
    23rd IEEE VLSI Test Symposium (VTS'05), 1
    Co-Authors: Jing Wang, Wangqi Qiu, S. Fancler, D.m.h. Walker, Ziding Yue, Weiping Shi
    Abstract:

    Excessive Power Supply Noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A Power Supply Noise estimation tool has been built and integrated into the compaction process. Compaction results for KLPG delay tests for ISCAS89 circuits under different Power grid environments are presented.