The Experts below are selected from a list of 123 Experts worldwide ranked by ideXlab platform
Dennis D. Giannacopoulos - One of the best experts on this subject based on the ideXlab platform.
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Field discontinuity refinement criteria and optimal discretizations in adaptive finite-element electromagnetic analysis for microelectronic system interconnections
IEEE Transactions on Magnetics, 2003Co-Authors: Dennis D. GiannacopoulosAbstract:The effectiveness of field-discontinuity refinement criteria for achieving optimal finite element discretizations is investigated. The criteria are first examined directly with finite-element solutions computed from optimally discretized systems. Subsequently, the optimality of the criteria are evaluated for practical adaptive finite-element electromagnetic analysis of Principal Device features in modern microelectronic system interconnection structures.
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Toward optimal error distributions in adaptive finite-element electromagnetic analysis for microelectronic interconnection structures
IEEE Transactions on Magnetics, 2002Co-Authors: Dennis D. GiannacopoulosAbstract:The effectiveness of finite-element refinement criteria for achieving optimal meshes based on error equidistribution principles are investigated with benchmark systems for the electromagnetic simulation of microelectronic system interconnection (MSI) features. The usefulness of the criteria are evaluated for adaptive finite-element electromagnetic analysis of Principal Device characteristics present in practical MSI structures, which are known to pose challenging problems in numerical modeling. The criteria with, potentially, the most significant implications for MSI electromagnetic simulation, are examined with finite-element solutions for the fundamental benchmark systems computed from both optimal and adaptively refined discretizations.
Hiroshi Iwai - One of the best experts on this subject based on the ideXlab platform.
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Analysis of threshold voltage variations of FinFETs relating to short channel effects
ECS Transactions, 2019Co-Authors: Yusuke Kobayashi, Kazuo Tsutsui, Kuniyuki Kakushima, Parhat Ahmet, V. Ramgopal Rao, Angada B. Sachid, Hiroshi IwaiAbstract:Clarification of robustness for threshold voltage (Δth) variation in FinFETs is very important. Vth variation (ΔVth) caused by fluctuations of some Principal Device parameters are evaluated, compared to the planar MOSFETs. However, the origin of ΔVth is complex in short channel Devices due to contribution of short channel effects (SCEs). Therefore, the origin of ΔVth is separated into two factors, that is, intrinsic factor which can be determined by Poisson's equation along M-O-S stack, called the 1D factor, and factors caused by SCEs, called 2D factors. The ΔVth is dominated by both factors on the planar MOSFETs, while it is dominated by the 2D factor on the FinFETs because the amount of spacer charge in the channel is small. Additionally, the Vth is studied in two advanced FinFET structures which show reduced SCEs.
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Analysis of Threshold Voltage Variations in Fin Field Effect Transistors
Key Engineering Materials, 2011Co-Authors: Kazuo Tsutsui, Yusuke Kobayashi, Kuniyuki Kakushima, Parhat Ahmet, V. Ramgopal Rao, Hiroshi IwaiAbstract:To conduct analyses of variability of threshold voltage (Vth) in FinFETs whose structures are based on the ITRS, sensitivity coefficients of variations of Vth caused by the fluctuation of Principal Device parameters were derived by Device simulation. The sensitivity coefficient correlated with each Device parameter was separated into two factors: one due to an intrinsic mechanism (1D factor) and another due to short-channel effects (2D factor). The 1D and 2D factors were found to cancel each other out in some cases, thereby reducing the sensitivity coefficient. Based on these results, FinFETs with various structures were examined and controlling short-channel effects was demonstrated to be an effective way to reduce the variation in the threshold voltage.
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Analysis of Threshold Voltage Variation in Fin Field Effect Transistors: Separation of Short Channel Effects
Japanese Journal of Applied Physics, 2010Co-Authors: Yusuke Kobayashi, Kazuo Tsutsui, Kuniyuki Kakushima, Parhat Ahmet, V. Ramgopal Rao, Hiroshi IwaiAbstract:The variation in the threshold voltage caused by fluctuations in a Device parameter is given by the product of a sensitivity coefficient and the fluctuation amount. In this paper, the sensitivity coefficient for each Device parameter was separated into two factors: one due to an intrinsic mechanism [one-dimensional (1D) factor] and another due to short-channel effects [two-dimensional (2D) factor]. Using this concept, the variations in the threshold voltage and the sensitivity coefficients in doped fin field effect transistors (FinFETs), undoped FinFETs and planar metal–oxide–semiconductor FETs (MOSFETs), whose structures are based on the ITRS, were evaluated for the fluctuations in the Principal Device parameters. It was found that the 2D factor rather than the 1D factor dominated the sensitivity coefficients, although the degree of domination varies between the fluctuating parameters. The 1D and 2D factors were found to cancel each other out, thereby reducing the sensitivity coefficient. Based on these results, FinFETs with various structures were examined and controlling short-channel effects was demonstrated to be an effective way to reduce the variation in the threshold voltage.
Jeffrey A. Davis - One of the best experts on this subject based on the ideXlab platform.
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Interconnect performance limits on gigascale integration (GSI)
Materials Chemistry and Physics, 1995Co-Authors: James D. Meindl, Jeffrey A. DavisAbstract:Future opportunities for gigascale integration (GSI) will be governed by a hierarchy of limits whose levels can be codified as: (i) fundamental, (ii) material, (iii) Device, (iv) circuit and (v) system. Performance limits on interconnects at all levels of this hierarchy are elucidated by plotting the square of reciprocal length of the interconnect versus the response time of the interconnect circuit. Fundamental and material limits are defined essentially by the time of flight of a lossless transmission line. The response time of a canonical distributed resistance-capacitance network imposes the Principal Device limit, while the dominant circuit limit is imposed by the response time of a driver-interconnect-load circuit. System limits are determined by the response time required from the longest global interconnect and hence chip size.
Giorgio Romanin-jacur - One of the best experts on this subject based on the ideXlab platform.
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The Multiple Connections Multi-Airport Ground Holding Problem: Models and Algorithms
Transportation Science, 1998Co-Authors: Lisa Navazio, Giorgio Romanin-jacurAbstract:In recent years air traffic has dramatically increased without a corresponding development of airports. Therefore, airports? limited capacity causes air traffic congestion and consequent expensive delays. The only strategy that can be applied in the short term with low investments aims at the optimal management of present resources; its Principal Device is Ground Holding, which consists of delaying an aircraft take off whenever it is foreseen it will not land in time because of congestion. We consider a traffic situation with "multiple connections" or "banking," i.e., the situation where some flights are assigned a set of "preceding" flights; no "successive" flight can start until all its preceding flights have landed. The problem consists of distributing delays to flights, so as to minimize the total delay cost, by respecting airport capacity, connections, and time constraints imposed by airlines. We construct an integer linear programming model and we solve it to optimality with CPLEX. Because the computation time is too high (hours) for real-world instances, we propose an alternative heuristic algorithm, which shows a very low computation time (seconds) and acceptable errors when tested on 30 realistic instances with strongly diversified data.
James D. Meindl - One of the best experts on this subject based on the ideXlab platform.
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Interconnect performance limits on gigascale integration (GSI)
Materials Chemistry and Physics, 1995Co-Authors: James D. Meindl, Jeffrey A. DavisAbstract:Future opportunities for gigascale integration (GSI) will be governed by a hierarchy of limits whose levels can be codified as: (i) fundamental, (ii) material, (iii) Device, (iv) circuit and (v) system. Performance limits on interconnects at all levels of this hierarchy are elucidated by plotting the square of reciprocal length of the interconnect versus the response time of the interconnect circuit. Fundamental and material limits are defined essentially by the time of flight of a lossless transmission line. The response time of a canonical distributed resistance-capacitance network imposes the Principal Device limit, while the dominant circuit limit is imposed by the response time of a driver-interconnect-load circuit. System limits are determined by the response time required from the longest global interconnect and hence chip size.