The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform

Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.

  • gated v sub dd a circuit technique to Reduce Leakage in deep submicron cache memories
    International Symposium on Low Power Electronics and Design, 2000
    Co-Authors: Michael D Powell, Kaushik Roy, Sehyun Yang, Babak Falsafi, T N Vijaykumar
    Abstract:

    Deep-submicron CMOS designs have resulted in large Leakage energy dissipation in microprocessors. While SRAM cells in on-chip cache memories always contribute to this Leakage, there is a large variability in active cell usage both within and across appli?cations. This paper explores an integrated architectural and circuit-level approach to reducing Leakage energy dissipation in instruc?tion caches. We propose, gated-V dd , a circuit-level technique to gate the supply voltage and Reduce Leakage in unused SRAM cells. Our results indicate that gated-V dd together with a novel resizable cache architecture Reduces energy-delay by 62% with minimal impact on performance.

  • mixed v sub th mvt cmos circuit design methodology for low power applications
    Design Automation Conference, 1999
    Co-Authors: Liqiong Wei, Zhanping Chen, Kaushik Roy
    Abstract:

    Dual threshold technique has been proposed to Reduce Leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance. Mixed-V/sub th/ (MVT) static CMOS design technique allows different thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique. In this paper, a methodology for MVT CMOS circuit design is presented. Different MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistor-level threshold assignment under performance constraints. Results indicate that MVT CMOS design technique can provide about 20% more Leakage reduction compared to the corresponding gate-level dual threshold technique.

  • design and optimization of dual threshold circuits for low voltage low power applications
    IEEE Transactions on Very Large Scale Integration Systems, 1999
    Co-Authors: Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C Johnson
    Abstract:

    Reduction in Leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to Reduce Leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best Leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general Leakage current model which has been verified by HSPICE simulations is used to estimate Leakage power. Results show that the dual-threshold technique is good for Leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the Leakage power can be Reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

  • design and optimization of low voltage high performance dual threshold cmos circuits
    Design Automation Conference, 1998
    Co-Authors: Liqiong Wei, Zhanping Chen, Mark C Johnson, Kaushik Roy
    Abstract:

    Reduction in Leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to Reduce Leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best Leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby Leakage current model which has been verified by IISPICE is used to estimate standby Leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby Leakage power savings for some ISCAS benchmarks can be more than 50%.

Zhanping Chen - One of the best experts on this subject based on the ideXlab platform.

  • mixed v sub th mvt cmos circuit design methodology for low power applications
    Design Automation Conference, 1999
    Co-Authors: Liqiong Wei, Zhanping Chen, Kaushik Roy
    Abstract:

    Dual threshold technique has been proposed to Reduce Leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance. Mixed-V/sub th/ (MVT) static CMOS design technique allows different thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique. In this paper, a methodology for MVT CMOS circuit design is presented. Different MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistor-level threshold assignment under performance constraints. Results indicate that MVT CMOS design technique can provide about 20% more Leakage reduction compared to the corresponding gate-level dual threshold technique.

  • design and optimization of dual threshold circuits for low voltage low power applications
    IEEE Transactions on Very Large Scale Integration Systems, 1999
    Co-Authors: Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C Johnson
    Abstract:

    Reduction in Leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to Reduce Leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best Leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general Leakage current model which has been verified by HSPICE simulations is used to estimate Leakage power. Results show that the dual-threshold technique is good for Leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the Leakage power can be Reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

  • design and optimization of low voltage high performance dual threshold cmos circuits
    Design Automation Conference, 1998
    Co-Authors: Zhanping Chen, Mark C Johnson, Vivek De
    Abstract:

    Reduction in Leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to Reduce Leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best Leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby Leakage current model which has been verified by IISPICE is used to estimate standby Leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby Leakage power savings for some ISCAS benchmarks can be more than 50%.

  • design and optimization of low voltage high performance dual threshold cmos circuits
    Design Automation Conference, 1998
    Co-Authors: Liqiong Wei, Zhanping Chen, Mark C Johnson, Kaushik Roy
    Abstract:

    Reduction in Leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to Reduce Leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best Leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby Leakage current model which has been verified by IISPICE is used to estimate standby Leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby Leakage power savings for some ISCAS benchmarks can be more than 50%.

Houman Homayoun - One of the best experts on this subject based on the ideXlab platform.

  • This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 MZZ-HVS: Multiple Sleep Modes Zig-Zag
    2016
    Co-Authors: Houman Homayoun, Alex Veidenbaum, Avesta Sasan, Hsincheng Yao, Shahin Golshan, Payam Heydari, Senior Member
    Abstract:

    Abstract—Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache Leakage. In addition, as technology mi-grates to smaller geometries, Leakage contribution to total power consumption increases faster than dynamic power, indicating that Leakage will be a major contributor to overall power consumption. This paper presents zig-zag share, a circuit technique to Reduce Leakage in SRAM peripherals by putting them into low-Leakage power sleep mode. The zig-zag share circuit is further extended to enable multiple sleep modes for cache peripherals. Each mode represents a trade-off between Leakage reduction and the wakeup delay. Using architectural control of multiple sleep modes, an inte-grated technique called MSleep-Share is proposed and applied in L1 and L2 caches. MSleep-share relies on cache miss information to guide Leakage control mechanism and switch peripheral circuit’s power mode. The results show Leakage reduction by up to 40 in deeply pipelined SRAM peripheral circuits, with small area over-head and small additional delay. This noticeable Leakage reduction translates to up to 85 % overall Leakage reduction in on-chip mem-ories. Index Terms—Horizontal and vertical sleep transistor sharing, Leakage power, Multiple sleep modes, SRAM peripheral. I

  • mzz hvs multiple sleep modes zig zag horizontal and vertical sleep transistor sharing to Reduce Leakage power in on chip sram peripheral circuits
    IEEE Transactions on Very Large Scale Integration Systems, 2011
    Co-Authors: Houman Homayoun, Alex Veidenbaum, Avesta Sasan, Hsincheng Yao, Shahin Golshan, Payam Heydari
    Abstract:

    Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache Leakage. In addition, as technology migrates to smaller geometries, Leakage contribution to total power consumption increases faster than dynamic power, indicating that Leakage will be a major contributor to overall power consumption. This paper presents zig-zag share, a circuit technique to Reduce Leakage in SRAM peripherals by putting them into low-Leakage power sleep mode. The zig-zag share circuit is further extended to enable multiple sleep modes for cache peripherals. Each mode represents a trade-off between Leakage reduction and the wakeup delay. Using architectural control of multiple sleep modes, an integrated technique called MSleep-Share is proposed and applied in L1 and L2 caches. MSleep-share relies on cache miss information to guide Leakage control mechanism and switch peripheral circuit's power mode. The results show Leakage reduction by up to 40× in deeply pipelined SRAM peripheral circuits, with small area overhead and small additional delay. This noticeable Leakage reduction translates to up to 85% overall Leakage reduction in on-chip memories.

  • MZZ-HVS: Multiple sleep modes zig-zag horizontal and vertical sleep transistor sharing to Reduce Leakage power in on-chip SRAM peripheral circuits,”IEEE Trans
    2011
    Co-Authors: Houman Homayoun, Avesta Sasan, Hsincheng Yao, Shahin Golshan, Payam Heydari, Er V. Veidenbaum, Senior Member
    Abstract:

    Abstract—Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache Leakage. In addition, as technology mi-grates to smaller geometries, Leakage contribution to total power consumption increases faster than dynamic power, indicating that Leakage will be a major contributor to overall power consumption. This paper presents zig-zag share, a circuit technique to Reduce Leakage in SRAM peripherals by putting them into low-Leakage power sleep mode. The zig-zag share circuit is further extended to enable multiple sleep modes for cache peripherals. Each mode represents a trade-off between Leakage reduction and the wakeup delay. Using architectural control of multiple sleep modes, an inte-grated technique called MSleep-Share is proposed and applied in L1 and L2 caches. MSleep-share relies on cache miss information to guide Leakage control mechanism and switch peripheral circuit’s power mode. The results show Leakage reduction by up to 40 in deeply pipelined SRAM peripheral circuits, with small area over-head and small additional delay. This noticeable Leakage reduc-tion translates to up to 85 % overall Leakage reduction in on-chip memories. Index Terms—Horizontal and vertical sleep transistor sharing, Leakage power, multiple sleep modes, SRAM peripheral. I

  • zz hvs zig zag horizontal and vertical sleep transistor sharing to Reduce Leakage power in on chip sram peripheral circuits
    International Conference on Computer Design, 2008
    Co-Authors: Houman Homayoun, Mohammad Makhzan, Alex Veidenbaum
    Abstract:

    Based on Recent studies peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache Leakage. In addition as technology migrate to smaller geometries, Leakage contribution to total power consumption increases faster than dynamic power, promoting Leakage as the largest power consumption factor. This paper proposes zig-zag share, a circuit technique to Reduce Leakage in SRAM peripheral. Using architectural control of zig-zag share, an integrated technique called Sleep-Share is proposed and applied in L1 and L2 caches. The results show Leakage reduction by up to 40X in deeply pipelined SRAM peripheral circuits, with only a 4% area overhead and small additional delay.

  • ZZ-HVS: Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage
    2008
    Co-Authors: Houman Homayoun, Mohammad Makhzan, Alex Veidenbaum
    Abstract:

    Abstract- Based on Recent studies peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache Leakage. In addition as technology migrate to smaller geometries, Leakage contribution to total power consumption increases faster than dynamic power, promoting Leakage as the largest power consumption factor. This paper proposes zig-zag share, a circuit technique to Reduce Leakage in SRAM peripheral. Using architectural control of zig-zag share, an integrated technique called Sleep-Share is proposed and applied in L1 and L2 caches. The results show Leakage reduction by up to 40X in deeply pipelined SRAM peripheral circuits, with only a 4 % area overhead and small additional delay. I

Liqiong Wei - One of the best experts on this subject based on the ideXlab platform.

  • mixed v sub th mvt cmos circuit design methodology for low power applications
    Design Automation Conference, 1999
    Co-Authors: Liqiong Wei, Zhanping Chen, Kaushik Roy
    Abstract:

    Dual threshold technique has been proposed to Reduce Leakage power in low voltage and low power circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance. Mixed-V/sub th/ (MVT) static CMOS design technique allows different thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique. In this paper, a methodology for MVT CMOS circuit design is presented. Different MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistor-level threshold assignment under performance constraints. Results indicate that MVT CMOS design technique can provide about 20% more Leakage reduction compared to the corresponding gate-level dual threshold technique.

  • design and optimization of dual threshold circuits for low voltage low power applications
    IEEE Transactions on Very Large Scale Integration Systems, 1999
    Co-Authors: Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C Johnson
    Abstract:

    Reduction in Leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to Reduce Leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best Leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general Leakage current model which has been verified by HSPICE simulations is used to estimate Leakage power. Results show that the dual-threshold technique is good for Leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the Leakage power can be Reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

  • design and optimization of low voltage high performance dual threshold cmos circuits
    Design Automation Conference, 1998
    Co-Authors: Liqiong Wei, Zhanping Chen, Mark C Johnson, Kaushik Roy
    Abstract:

    Reduction in Leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to Reduce Leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best Leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby Leakage current model which has been verified by IISPICE is used to estimate standby Leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby Leakage power savings for some ISCAS benchmarks can be more than 50%.

Alex Veidenbaum - One of the best experts on this subject based on the ideXlab platform.

  • This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 MZZ-HVS: Multiple Sleep Modes Zig-Zag
    2016
    Co-Authors: Houman Homayoun, Alex Veidenbaum, Avesta Sasan, Hsincheng Yao, Shahin Golshan, Payam Heydari, Senior Member
    Abstract:

    Abstract—Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache Leakage. In addition, as technology mi-grates to smaller geometries, Leakage contribution to total power consumption increases faster than dynamic power, indicating that Leakage will be a major contributor to overall power consumption. This paper presents zig-zag share, a circuit technique to Reduce Leakage in SRAM peripherals by putting them into low-Leakage power sleep mode. The zig-zag share circuit is further extended to enable multiple sleep modes for cache peripherals. Each mode represents a trade-off between Leakage reduction and the wakeup delay. Using architectural control of multiple sleep modes, an inte-grated technique called MSleep-Share is proposed and applied in L1 and L2 caches. MSleep-share relies on cache miss information to guide Leakage control mechanism and switch peripheral circuit’s power mode. The results show Leakage reduction by up to 40 in deeply pipelined SRAM peripheral circuits, with small area over-head and small additional delay. This noticeable Leakage reduction translates to up to 85 % overall Leakage reduction in on-chip mem-ories. Index Terms—Horizontal and vertical sleep transistor sharing, Leakage power, Multiple sleep modes, SRAM peripheral. I

  • mzz hvs multiple sleep modes zig zag horizontal and vertical sleep transistor sharing to Reduce Leakage power in on chip sram peripheral circuits
    IEEE Transactions on Very Large Scale Integration Systems, 2011
    Co-Authors: Houman Homayoun, Alex Veidenbaum, Avesta Sasan, Hsincheng Yao, Shahin Golshan, Payam Heydari
    Abstract:

    Recent studies show that peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache Leakage. In addition, as technology migrates to smaller geometries, Leakage contribution to total power consumption increases faster than dynamic power, indicating that Leakage will be a major contributor to overall power consumption. This paper presents zig-zag share, a circuit technique to Reduce Leakage in SRAM peripherals by putting them into low-Leakage power sleep mode. The zig-zag share circuit is further extended to enable multiple sleep modes for cache peripherals. Each mode represents a trade-off between Leakage reduction and the wakeup delay. Using architectural control of multiple sleep modes, an integrated technique called MSleep-Share is proposed and applied in L1 and L2 caches. MSleep-share relies on cache miss information to guide Leakage control mechanism and switch peripheral circuit's power mode. The results show Leakage reduction by up to 40× in deeply pipelined SRAM peripheral circuits, with small area overhead and small additional delay. This noticeable Leakage reduction translates to up to 85% overall Leakage reduction in on-chip memories.

  • zz hvs zig zag horizontal and vertical sleep transistor sharing to Reduce Leakage power in on chip sram peripheral circuits
    International Conference on Computer Design, 2008
    Co-Authors: Houman Homayoun, Mohammad Makhzan, Alex Veidenbaum
    Abstract:

    Based on Recent studies peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache Leakage. In addition as technology migrate to smaller geometries, Leakage contribution to total power consumption increases faster than dynamic power, promoting Leakage as the largest power consumption factor. This paper proposes zig-zag share, a circuit technique to Reduce Leakage in SRAM peripheral. Using architectural control of zig-zag share, an integrated technique called Sleep-Share is proposed and applied in L1 and L2 caches. The results show Leakage reduction by up to 40X in deeply pipelined SRAM peripheral circuits, with only a 4% area overhead and small additional delay.

  • ZZ-HVS: Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage
    2008
    Co-Authors: Houman Homayoun, Mohammad Makhzan, Alex Veidenbaum
    Abstract:

    Abstract- Based on Recent studies peripheral circuit (including decoders, wordline drivers, input and output drivers) constitutes a large portion of the cache Leakage. In addition as technology migrate to smaller geometries, Leakage contribution to total power consumption increases faster than dynamic power, promoting Leakage as the largest power consumption factor. This paper proposes zig-zag share, a circuit technique to Reduce Leakage in SRAM peripheral. Using architectural control of zig-zag share, an integrated technique called Sleep-Share is proposed and applied in L1 and L2 caches. The results show Leakage reduction by up to 40X in deeply pipelined SRAM peripheral circuits, with only a 4 % area overhead and small additional delay. I