The Experts below are selected from a list of 810 Experts worldwide ranked by ideXlab platform

Seth Copen Goldstein - One of the best experts on this subject based on the ideXlab platform.

  • Published In A Better Global Progressive Register Allocator
    2015
    Co-Authors: David Ryan Koes, Seth Copen Goldstein
    Abstract:

    We present an improvement to the simultaneous heuristic Allocator component of the global pro-gressive Register Allocator described in our previous work [Koes06]. Our improved Allocator de-composes the control flow graph into linear traces which are allocated in the same manner as a single basic block. We investigate two methods for handling the control flow within the traces both of which produce better quality allocations than the simultaneous heuristic Allocator

  • Progressive Register Allocator
    2012
    Co-Authors: David Ryan Koes, Seth Copen Goldstein
    Abstract:

    We present an improvement to the simultaneous heuristic Allocator component of the global progressive Register Allocator described in our previous work [Koes06]. Our improved Allocator decomposes the control flow graph into linear traces which are allocated in the same manner as a single basic block. We investigate two methods for handling the control flow within the traces both of which produce better quality allocations than the simultaneous heuristic Allocator. KEYWORDS: Register Allocation; Progressive Solver

  • What’s Wrong with Graph Coloring?
    2008
    Co-Authors: David Koes, Seth Copen Goldstein
    Abstract:

    Graph coloring is the de facto standard technique for Register allocation within a compiler. In this paper we examine the intuition that a better coloring algorithm results in better Register allocation. By replacing the coloring phase of thegcc compiler’s Register Allocator with an optimal coloring algorithm, we demonstrate both the importance of extending the graph coloring model to better express the costs of allocation decisions and the unsuitability of a pure graph coloring model of Register allocation.

  • a global progressive Register Allocator
    Programming Language Design and Implementation, 2006
    Co-Authors: David Ryan Koes, Seth Copen Goldstein
    Abstract:

    This paper describes a global progressive Register Allocator, a Register Allocator that uses an expressive model of the Register allocation problem to quickly find a good allocation and then progressively find better allocations until a provably optimal solution is found or a preset time limit is reached. The key contributions of this paper are an expressive model of global Register allocation based on multicommodity network flows that explicitly represents spill code optimization, Register preferences, copy insertion, and constant rematerialization; two fast, but effective, heuristic Allocators based on this model; and a more elaborate progressive Allocator that uses Lagrangian relaxation to compute the optimality of its allocations. Our progressive Allocator demonstrates code size improvements as large as 16.75% compared to a traditional graph Allocator. On average, we observe an initial improvement of 3.47%, which increases progressively to 6.84% as more time is permitted for compilation.

  • A Better Global Progressive Register Allocator
    2006
    Co-Authors: David Ryan Koes, Seth Copen Goldstein
    Abstract:

    We present an improvement to the simultaneous heuristic Allocator component of the global progressive Register Allocator described in our previous work [Koes06]. Our improved Allocator decomposes the control flow graph into linear traces which are allocated in the same manner as a single basic block. We investigate two methods for handling the control flow within the traces both of which produce better quality allocations than the simultaneous heuristic Allocator.

Heiko Falk - One of the best experts on this subject based on the ideXlab platform.

  • WCET-aware Register Allocation based on Integer-Linear Programming
    2012
    Co-Authors: Heiko Falk, Norman Schmitz, Florian Schmoll
    Abstract:

    Abstract—Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the most important optimizations is Register allocation. Many compilers heuristically decide when and where to spill a Register to memory, without having a clear understanding of the impact of such spill code on a program’s runtime. This paper presents an integer-linear programming (ILP) based Register Allocator that uses precise worst-case execution time (WCET) models. Using this WCET timing data, the compiler avoids spill code generation along the critical path defining a program’s WCET. To the best of our knowledge, this paper is the first one to present a WCET-aware ILP-based Register Allocator. Our results underline the effectiveness of the proposed techniques. For a total of 55 realistic benchmarks, we reduced WCETs by 20.2 % on average and ACETs by 14%, compared to a standard graph coloring Allocator. Furthermore, our ILP-based Register Allocator outperforms a WCET-aware graph coloring Allocator by more than a factor of two for the considered benchmarks, while requiring less runtime

  • Algorithms, Performance
    2012
    Co-Authors: Heiko Falk
    Abstract:

    Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the most important optimizations is Register allocation. Many compilers heuristically decide when and where to spill a Register to memory, without having a clear understanding of the impact of such spill code on a program’s run time. This paper extends a graph coloring Register Allocator such that it uses precise worst-case execution time (WCET) models. Using this WCET timing data, the compiler tries to avoid spill code generation along the critical path defining a program’s WCET. To the best of our knowledge, this paper is the first one to present a WCET-aware Register Allocator. Our results underline the effectiveness of the proposed techniques. For a total of 46 realistic benchmarks, we reduced WCETs by 31.2 % on average. Additionally, the runtimes of our WCET-aware Register Allocator still remain acceptable

  • wcet aware Register allocation based on graph coloring
    Design Automation Conference, 2009
    Co-Authors: Heiko Falk
    Abstract:

    Current compilers lack precise timing models guiding their built-in optimizations. Hence, compilers apply ad-hoc heuristics during optimization to improve code quality. One of the most important optimizations is Register allocation. Many compilers heuristically decide when and where to spill a Register to memory, without having a clear understanding of the impact of such spill code on a program's run time. This paper extends a graph coloring Register Allocator such that it uses precise worst-case execution time (WCET) models. Using this WCET timing data, the compiler tries to avoid spill code generation along the critical path defining a program's WCET. To the best of our knowledge, this paper is the first one to present a WCET-aware Register Allocator. Our results underline the effectiveness of the proposed techniques. For a total of 46 realistic benchmarks, we reduced WCETs by 31.2% on average. Additionally, the runtimes of our WCET-aware Register Allocator still remain acceptable.

David Ryan Koes - One of the best experts on this subject based on the ideXlab platform.

  • Published In A Better Global Progressive Register Allocator
    2015
    Co-Authors: David Ryan Koes, Seth Copen Goldstein
    Abstract:

    We present an improvement to the simultaneous heuristic Allocator component of the global pro-gressive Register Allocator described in our previous work [Koes06]. Our improved Allocator de-composes the control flow graph into linear traces which are allocated in the same manner as a single basic block. We investigate two methods for handling the control flow within the traces both of which produce better quality allocations than the simultaneous heuristic Allocator

  • Progressive Register Allocator
    2012
    Co-Authors: David Ryan Koes, Seth Copen Goldstein
    Abstract:

    We present an improvement to the simultaneous heuristic Allocator component of the global progressive Register Allocator described in our previous work [Koes06]. Our improved Allocator decomposes the control flow graph into linear traces which are allocated in the same manner as a single basic block. We investigate two methods for handling the control flow within the traces both of which produce better quality allocations than the simultaneous heuristic Allocator. KEYWORDS: Register Allocation; Progressive Solver

  • a global progressive Register Allocator
    Programming Language Design and Implementation, 2006
    Co-Authors: David Ryan Koes, Seth Copen Goldstein
    Abstract:

    This paper describes a global progressive Register Allocator, a Register Allocator that uses an expressive model of the Register allocation problem to quickly find a good allocation and then progressively find better allocations until a provably optimal solution is found or a preset time limit is reached. The key contributions of this paper are an expressive model of global Register allocation based on multicommodity network flows that explicitly represents spill code optimization, Register preferences, copy insertion, and constant rematerialization; two fast, but effective, heuristic Allocators based on this model; and a more elaborate progressive Allocator that uses Lagrangian relaxation to compute the optimality of its allocations. Our progressive Allocator demonstrates code size improvements as large as 16.75% compared to a traditional graph Allocator. On average, we observe an initial improvement of 3.47%, which increases progressively to 6.84% as more time is permitted for compilation.

  • A Better Global Progressive Register Allocator
    2006
    Co-Authors: David Ryan Koes, Seth Copen Goldstein
    Abstract:

    We present an improvement to the simultaneous heuristic Allocator component of the global progressive Register Allocator described in our previous work [Koes06]. Our improved Allocator decomposes the control flow graph into linear traces which are allocated in the same manner as a single basic block. We investigate two methods for handling the control flow within the traces both of which produce better quality allocations than the simultaneous heuristic Allocator.

  • A Global Progressive Register Allocator
    ACM Press, 2006
    Co-Authors: David Ryan Koes, Seth Copen Goldstein
    Abstract:

    We present an improvement to the simultaneous heuristic Allocator component of the global progressive Register Allocator described in our previous work [Koes06]. Our improved Allocator decomposes the control flow graph into linear traces which are allocated in the same manner as a single basic block. We investigate two methods for handling the control flow within the traces both of which produce better quality allocations than the simultaneous heuristic Allocator

Michael Franz - One of the best experts on this subject based on the ideXlab platform.

  • linear scan Register allocation on ssa form
    Symposium on Code Generation and Optimization, 2010
    Co-Authors: Christian Wimmer, Michael Franz
    Abstract:

    The linear scan algorithm for Register allocation provides a good Register assignment with a low compilation overhead and is thus frequently used for just-in-time compilers. Although most of these compilers use static single assignment (SSA) form, the algorithm has not yet been applied on SSA form, i.e., SSA form is usually deconstructed before Register allocation. However, the structural properties of SSA form can be used to simplify the algorithm. With only one definition per variable, lifetime intervals (the main data structure) can be constructed without data flow analysis. During allocation, some tests of interval intersection can be skipped because SSA form guarantees non-intersection. Finally, deconstruction of SSA form after Register allocation can be integrated into the resolution phase of the Register Allocator without much additional code. We modified the linear scan Register Allocator of the Java HotSpot client compiler so that it operates on SSA form. The evaluation shows that our simpler and faster version generates equally good or slightly better machine code.

Christian Wimmer - One of the best experts on this subject based on the ideXlab platform.

  • linear scan Register allocation on ssa form
    Symposium on Code Generation and Optimization, 2010
    Co-Authors: Christian Wimmer, Michael Franz
    Abstract:

    The linear scan algorithm for Register allocation provides a good Register assignment with a low compilation overhead and is thus frequently used for just-in-time compilers. Although most of these compilers use static single assignment (SSA) form, the algorithm has not yet been applied on SSA form, i.e., SSA form is usually deconstructed before Register allocation. However, the structural properties of SSA form can be used to simplify the algorithm. With only one definition per variable, lifetime intervals (the main data structure) can be constructed without data flow analysis. During allocation, some tests of interval intersection can be skipped because SSA form guarantees non-intersection. Finally, deconstruction of SSA form after Register allocation can be integrated into the resolution phase of the Register Allocator without much additional code. We modified the linear scan Register Allocator of the Java HotSpot client compiler so that it operates on SSA form. The evaluation shows that our simpler and faster version generates equally good or slightly better machine code.

  • ABSTRACT Optimized Interval Splitting in a Linear Scan Register Allocator ∗
    2008
    Co-Authors: Christian Wimmer, Hanspeter Mössenböck
    Abstract:

    We present an optimized implementation of the linear scan Register allocation algorithm for Sun Microsystems ’ Java HotSpot TM client compiler. Linear scan Register allocation is especially suitable for just-in-time compilers because it is faster than the common graph-coloring approach and yields results of nearly the same quality. Our Allocator improves the basic linear scan algorithm by adding more advanced optimizations: It makes use of lifetime holes, splits intervals if the Register pressure is too high, and models Register constraints of the target architecture with fixed intervals. Three additional optimizations move split positions out of loops, remove Register-to-Register moves and eliminate unnecessary spill stores. Interval splitting is based on use positions, which also capture the kind of use and whether an operand is needed in a Register or not. This avoids the reservation of a scratch Register. Benchmark results prove the efficiency of the linear scan algorithm: While the compilation speed is equal to the old local Register Allocator that is part of the Sun JDK 5.0, integer benchmarks execute about 15 % faster. Floating-point benchmarks show the high impact of the Intel SSE2 extensions on the speed of numeric Java applications: With the new SSE2 support enabled, SPECjvm98 executes 25 % faster compared with the current Sun JDK 5.0

  • Optimized interval splitting in a linear scan Register Allocator
    2005
    Co-Authors: Christian Wimmer, Hanspeter Mössenböck
    Abstract:

    We present an optimized implementation of the linear scan Register allocation algorithm for Sun Microsystems ’ Java HotSpot TM client compiler. Linear scan Register allocation is especially suitable for just-in-time compilers because it is faster than the common graph-coloring approach and yields results of nearly the same quality. Our Allocator improves the basic linear scan algorithm by adding more advanced optimizations: It makes use of lifetime holes, splits intervals if the Register pressure is too high, and models Register constraints of the target architecture with fixed intervals. Three additional optimizations move split positions out of loops, remove Register-to-Register moves and eliminate unnecessary spill stores. Interval splitting is based on use positions, which also capture the kind of use and whether an operand is needed in a Register or not. This avoids the reservation of a scratch Register. Benchmark results prove the efficiency of the linear scan algorithm: While the compilation speed is equal to the old local Register Allocator that is part of the Sun JDK 5.0, integer benchmarks execute about 15 % faster. Floating-point benchmarks show the high impact of the Intel SSE2 extensions on the speed of numeric Java applications: With the new SSE2 support enabled, SPECjvm98 executes 25 % faster compared with the current Sun JDK 5.0