The Experts below are selected from a list of 177 Experts worldwide ranked by ideXlab platform
Shinichi Yorozu - One of the best experts on this subject based on the ideXlab platform.
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Bit-Error-Rate Measurements of RSFQ Shift Register Memories
IEEE Transactions on Applied Superconductivity, 2007Co-Authors: Tomohiro Hikida, Kan Fujiwara, Hirotaka Terai, Akira Fujimaki, Nobuyuki Yoshikawa, Shinichi YorozuAbstract:Error rates of rapid-single-flux-quantum (RSFQ) shift Register memories were investigated using a high-speed error-rate measurement system in order to demonstrate their reliability and stability. We designed and implemented an 8 times 8-bit shift Register Memory using the CONNECT cell library and the SRL 2.5 kA/cm2 Nb process. The total number of Josephson junctions including the test system is 4184, and the circuit area is 2.1 mm times 3.2 mm. We measured the error rates of every storage node by reading out the data 216 times at the clock frequency of 16 GHz. The measured error rates were lower than 10-10 with DC bias margin better than plusmn5%.
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High-speed test of SFQ-shift Register files using PTL wiring
Physica C-superconductivity and Its Applications, 2004Co-Authors: K. Fujiwara, Shinichi Yorozu, Nobuyuki Yoshikawa, Y. Yamashiro, Yoshihito Hashimoto, H. Terai, Akira FujimakiAbstract:Abstract We have been developing an SFQ shift Register Memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our Memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift Register Memory is composed of shift Registers with non-destructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the Memory system at high speed. The tested circuit is a 4-byte shift Register file, where four kinds of wiring circuits are used between a decoder and shift Registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the Memory system. We have used the NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library.
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High-speed test of SFQ-shift Register files using PTL wiring
Physica C: Superconductivity, 2004Co-Authors: K. Fujiwara, Shinichi Yorozu, Y. Yamashiro, Yoshihito Hashimoto, H. Terai, N. Yoshikawa, A. FujimakiAbstract:We have been developing an SFQ shift Register Memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our Memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift Register Memory is composed of shift Registers with nondestructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the Memory system at high speed. The tested circuit is a 4-byte shift Register file, where four kinds of wiring circuits are used between a decoder and shift Registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the Memory system. We have used the NEC 2.5 kA/cm(2) Nb standard process and the CONNECT cell library. (C) 2004 Elsevier B.V. All rights reserved
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design and high speed test of 4 8 bit single flux quantum shift Register files
Superconductor Science and Technology, 2003Co-Authors: K. Fujiwara, Akira Fujimaki, Nobuyuki Yoshikawa, Y. Yamashiro, H. Terai, Shinichi YorozuAbstract:In the realization of large-scale single-flux-quantum (SFQ) digital systems, one of the most serious problems is the lack of high-density and high-speed memories. We have been developing random access memories using SFQ shift Registers, which are one candidate to solve the Memory problem in the SFQ digital system because of their high throughput and short access time. In this paper we have designed and tested a (4 × 8)-bit SFQ shift Register file as a demonstration of the SFQ shift Register Memory system. Its target clock frequency is 20 GHz assuming an NEC 2.5 kA cm−2 Nb standard process. In the test, we have confirmed that 8-bit dual-rail data can be loaded to appropriate shift Registers specified by 2-bit address data. We have also verified that the loaded data are read out and written back to the same shift Register at high speed. A tested dc bias margin at 20 GHz is ±5%.
K. Fujiwara - One of the best experts on this subject based on the ideXlab platform.
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High-speed test of SFQ-shift Register files using PTL wiring
Physica C-superconductivity and Its Applications, 2004Co-Authors: K. Fujiwara, Shinichi Yorozu, Nobuyuki Yoshikawa, Y. Yamashiro, Yoshihito Hashimoto, H. Terai, Akira FujimakiAbstract:Abstract We have been developing an SFQ shift Register Memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our Memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift Register Memory is composed of shift Registers with non-destructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the Memory system at high speed. The tested circuit is a 4-byte shift Register file, where four kinds of wiring circuits are used between a decoder and shift Registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the Memory system. We have used the NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library.
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High-speed test of SFQ-shift Register files using PTL wiring
Physica C: Superconductivity, 2004Co-Authors: K. Fujiwara, Shinichi Yorozu, Y. Yamashiro, Yoshihito Hashimoto, H. Terai, N. Yoshikawa, A. FujimakiAbstract:We have been developing an SFQ shift Register Memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our Memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift Register Memory is composed of shift Registers with nondestructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the Memory system at high speed. The tested circuit is a 4-byte shift Register file, where four kinds of wiring circuits are used between a decoder and shift Registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the Memory system. We have used the NEC 2.5 kA/cm(2) Nb standard process and the CONNECT cell library. (C) 2004 Elsevier B.V. All rights reserved
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design and high speed test of 4 8 bit single flux quantum shift Register files
Superconductor Science and Technology, 2003Co-Authors: K. Fujiwara, Akira Fujimaki, Nobuyuki Yoshikawa, Y. Yamashiro, H. Terai, Shinichi YorozuAbstract:In the realization of large-scale single-flux-quantum (SFQ) digital systems, one of the most serious problems is the lack of high-density and high-speed memories. We have been developing random access memories using SFQ shift Registers, which are one candidate to solve the Memory problem in the SFQ digital system because of their high throughput and short access time. In this paper we have designed and tested a (4 × 8)-bit SFQ shift Register file as a demonstration of the SFQ shift Register Memory system. Its target clock frequency is 20 GHz assuming an NEC 2.5 kA cm−2 Nb standard process. In the test, we have confirmed that 8-bit dual-rail data can be loaded to appropriate shift Registers specified by 2-bit address data. We have also verified that the loaded data are read out and written back to the same shift Register at high speed. A tested dc bias margin at 20 GHz is ±5%.
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Design and component test of SFQ shift Register memories
IEEE Transactions on Appiled Superconductivity, 2003Co-Authors: K. Fujiwara, Y. Yamashiro, H. Hoshina, Nobuyuki YoshikawaAbstract:The lack of a high-density and high-speed Memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister Memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift Register Memory, which is usable for the high-speed Register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift Registers and a packet decoder that switches a high-speed serial data stream into the specified shift Register. The target clock frequency is 16 GHz assuming 2.5 kA/cm/sup 2/ Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the Memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.
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Design and component test of RSFQ packet decoders for shift Register memories
Physica C-superconductivity and Its Applications, 2002Co-Authors: K. Fujiwara, H. Hoshina, J. Koshiyama, Nobuyuki YoshikawaAbstract:Abstract We show a design framework of shift Register memories, which is usable for the high-speed Register file of the RSFQ microprocessor. The proposed shift Register Memory consists of an array of shift Registers and a packet decoder that switches a high-speed serial data stream into the destined shift Register. A target clock frequency is 20 GHz assuming 1 kA/cm 2 Nb standard process. A concept of data-drive self-timing (DDST) is employed to reduce the timing difficulty in the synchronized RSFQ circuit. In this paper we also show the design details of the DDST RSFQ packet decoder, which is composed of one-to-two DDST RSFQ packet switches. A D3 flip-flop, a main building element of the one-to-two DDST RSFQ packet switch, is newly developed as a non-destructive Memory cell. The low speed test shows that the DC bias margin of the D3 flip-flop is ±32%. We have also estimated the latency and the circuit area of the DDST packet decoder.
Nobuyuki Yoshikawa - One of the best experts on this subject based on the ideXlab platform.
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Bit-Error-Rate Measurements of RSFQ Shift Register Memories
IEEE Transactions on Applied Superconductivity, 2007Co-Authors: Tomohiro Hikida, Kan Fujiwara, Hirotaka Terai, Akira Fujimaki, Nobuyuki Yoshikawa, Shinichi YorozuAbstract:Error rates of rapid-single-flux-quantum (RSFQ) shift Register memories were investigated using a high-speed error-rate measurement system in order to demonstrate their reliability and stability. We designed and implemented an 8 times 8-bit shift Register Memory using the CONNECT cell library and the SRL 2.5 kA/cm2 Nb process. The total number of Josephson junctions including the test system is 4184, and the circuit area is 2.1 mm times 3.2 mm. We measured the error rates of every storage node by reading out the data 216 times at the clock frequency of 16 GHz. The measured error rates were lower than 10-10 with DC bias margin better than plusmn5%.
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High-speed test of SFQ-shift Register files using PTL wiring
Physica C-superconductivity and Its Applications, 2004Co-Authors: K. Fujiwara, Shinichi Yorozu, Nobuyuki Yoshikawa, Y. Yamashiro, Yoshihito Hashimoto, H. Terai, Akira FujimakiAbstract:Abstract We have been developing an SFQ shift Register Memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our Memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift Register Memory is composed of shift Registers with non-destructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the Memory system at high speed. The tested circuit is a 4-byte shift Register file, where four kinds of wiring circuits are used between a decoder and shift Registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the Memory system. We have used the NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library.
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design and high speed test of 4 8 bit single flux quantum shift Register files
Superconductor Science and Technology, 2003Co-Authors: K. Fujiwara, Akira Fujimaki, Nobuyuki Yoshikawa, Y. Yamashiro, H. Terai, Shinichi YorozuAbstract:In the realization of large-scale single-flux-quantum (SFQ) digital systems, one of the most serious problems is the lack of high-density and high-speed memories. We have been developing random access memories using SFQ shift Registers, which are one candidate to solve the Memory problem in the SFQ digital system because of their high throughput and short access time. In this paper we have designed and tested a (4 × 8)-bit SFQ shift Register file as a demonstration of the SFQ shift Register Memory system. Its target clock frequency is 20 GHz assuming an NEC 2.5 kA cm−2 Nb standard process. In the test, we have confirmed that 8-bit dual-rail data can be loaded to appropriate shift Registers specified by 2-bit address data. We have also verified that the loaded data are read out and written back to the same shift Register at high speed. A tested dc bias margin at 20 GHz is ±5%.
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Design and component test of SFQ shift Register memories
IEEE Transactions on Appiled Superconductivity, 2003Co-Authors: K. Fujiwara, Y. Yamashiro, H. Hoshina, Nobuyuki YoshikawaAbstract:The lack of a high-density and high-speed Memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister Memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift Register Memory, which is usable for the high-speed Register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift Registers and a packet decoder that switches a high-speed serial data stream into the specified shift Register. The target clock frequency is 16 GHz assuming 2.5 kA/cm/sup 2/ Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the Memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.
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Design and component test of RSFQ packet decoders for shift Register memories
Physica C-superconductivity and Its Applications, 2002Co-Authors: K. Fujiwara, H. Hoshina, J. Koshiyama, Nobuyuki YoshikawaAbstract:Abstract We show a design framework of shift Register memories, which is usable for the high-speed Register file of the RSFQ microprocessor. The proposed shift Register Memory consists of an array of shift Registers and a packet decoder that switches a high-speed serial data stream into the destined shift Register. A target clock frequency is 20 GHz assuming 1 kA/cm 2 Nb standard process. A concept of data-drive self-timing (DDST) is employed to reduce the timing difficulty in the synchronized RSFQ circuit. In this paper we also show the design details of the DDST RSFQ packet decoder, which is composed of one-to-two DDST RSFQ packet switches. A D3 flip-flop, a main building element of the one-to-two DDST RSFQ packet switch, is newly developed as a non-destructive Memory cell. The low speed test shows that the DC bias margin of the D3 flip-flop is ±32%. We have also estimated the latency and the circuit area of the DDST packet decoder.
David N Beratan - One of the best experts on this subject based on the ideXlab platform.
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Design of a Molecular Memory Device: The Electron Transfer Shift Register Memory
1993Co-Authors: David N BeratanAbstract:A molecular shift Register Memory at the molecular level is described. The Memory elements consist of molecules can exit in either an oxidized or reduced state and the bits are shifted between the cells with photoinduced electron transfer reactions.
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Tunneling Pathways In Proteins: From Biology To Molecular Electronics
[1990] Proceedings of the Twelfth Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 1Co-Authors: Jose N Onuchic, David N BeratanAbstract:We describe how we are calculating tunneling matrix elements for electron transfer in proteins. The concept of a tunneling pathway is introduced and we describe its importance in mediating this coupling. Finally we comment on how, using our knowledge about electron transfer reactions, we designed a molecular shift Register Memory.
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Ultrasmall memories based on electron transfer reactions
Images of the Twenty-First Century. Proceedings of the Annual International Engineering in Medicine and Biology Society, 1Co-Authors: David N Beratan, John J. Hopfield, Jose N OnuchicAbstract:Summary form only given. An electronic shift Register Memory at the molecular level is described. The Memory elements are based on a chain of electron transfer molecules, and the information is shifted by photoinduced electron transfer reactions. This device integrates designed electronic molecules onto a very-large-scale integrated (silicon microelectronic) substrate, providing an example of a molecular electronic device. >
Akira Fujimaki - One of the best experts on this subject based on the ideXlab platform.
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Bit-Error-Rate Measurements of RSFQ Shift Register Memories
IEEE Transactions on Applied Superconductivity, 2007Co-Authors: Tomohiro Hikida, Kan Fujiwara, Hirotaka Terai, Akira Fujimaki, Nobuyuki Yoshikawa, Shinichi YorozuAbstract:Error rates of rapid-single-flux-quantum (RSFQ) shift Register memories were investigated using a high-speed error-rate measurement system in order to demonstrate their reliability and stability. We designed and implemented an 8 times 8-bit shift Register Memory using the CONNECT cell library and the SRL 2.5 kA/cm2 Nb process. The total number of Josephson junctions including the test system is 4184, and the circuit area is 2.1 mm times 3.2 mm. We measured the error rates of every storage node by reading out the data 216 times at the clock frequency of 16 GHz. The measured error rates were lower than 10-10 with DC bias margin better than plusmn5%.
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High-speed test of SFQ-shift Register files using PTL wiring
Physica C-superconductivity and Its Applications, 2004Co-Authors: K. Fujiwara, Shinichi Yorozu, Nobuyuki Yoshikawa, Y. Yamashiro, Yoshihito Hashimoto, H. Terai, Akira FujimakiAbstract:Abstract We have been developing an SFQ shift Register Memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our Memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift Register Memory is composed of shift Registers with non-destructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the Memory system at high speed. The tested circuit is a 4-byte shift Register file, where four kinds of wiring circuits are used between a decoder and shift Registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the Memory system. We have used the NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library.
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design and high speed test of 4 8 bit single flux quantum shift Register files
Superconductor Science and Technology, 2003Co-Authors: K. Fujiwara, Akira Fujimaki, Nobuyuki Yoshikawa, Y. Yamashiro, H. Terai, Shinichi YorozuAbstract:In the realization of large-scale single-flux-quantum (SFQ) digital systems, one of the most serious problems is the lack of high-density and high-speed memories. We have been developing random access memories using SFQ shift Registers, which are one candidate to solve the Memory problem in the SFQ digital system because of their high throughput and short access time. In this paper we have designed and tested a (4 × 8)-bit SFQ shift Register file as a demonstration of the SFQ shift Register Memory system. Its target clock frequency is 20 GHz assuming an NEC 2.5 kA cm−2 Nb standard process. In the test, we have confirmed that 8-bit dual-rail data can be loaded to appropriate shift Registers specified by 2-bit address data. We have also verified that the loaded data are read out and written back to the same shift Register at high speed. A tested dc bias margin at 20 GHz is ±5%.
