The Experts below are selected from a list of 42639 Experts worldwide ranked by ideXlab platform
Earl E. Swartzlander - One of the best experts on this subject based on the ideXlab platform.
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DFT - Quadruple Time Redundancy Adders
2003Co-Authors: Whitney J. Townsend, Jacob A. Abraham, Earl E. SwartzlanderAbstract:This paper presents a concurrent error correcting adder design employing fault masking through a combination of Time and hardware Redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Tripple Modular Redundancy adder, and a Time Shared Triple Modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time Shared Triple Modular Redundancy to which it is most closely related, Quadruple Time Redundancy results in a 40% - 55% reduction in hardware complexity while incurring a reasonable delay increase.
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quadruple Time Redundancy adders
Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2003Co-Authors: Whitney J. Townsend, Jacob A. Abraham, Earl E. SwartzlanderAbstract:This paper presents a concurrent error correcting adder design employing fault masking through a combination of Time and hardware Redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Tripple Modular Redundancy adder, and a Time Shared Triple Modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time Shared Triple Modular Redundancy to which it is most closely related, Quadruple Time Redundancy results in a 40% - 55% reduction in hardware complexity while incurring a reasonable delay increase.
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Quadruple Time Redundancy adders [error correcting adder]
Proceedings. 16th IEEE Symposium on Computer Arithmetic, 1Co-Authors: Whitney J. Townsend, Jacob A. Abraham, Earl E. SwartzlanderAbstract:This paper presents a concurrent error correcting adder design employing fault masking through a combination of Time and hardware Redundancy. This new method, quadruple Time Redundancy, is compared with a non-redundant adder, a triple modular Redundancy adder, and a Time shared triple modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time shared triple modular Redundancy to which it is most closely related, quadruple Time Redundancy results in a 40%-55% reduction in hardware complexity while incurring a reasonable delay increase.
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Time Redundancy for error detecting neural networks
Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI), 1Co-Authors: Yuang Ming Hsu, Vincenzo Piuri, Earl E. SwartzlanderAbstract:Concurrent error detection at an architectural level is often a basic requirement to achieve fault tolerance in neural networks for mission-critical applications. Time Redundancy allows for concurrent error detection with low circuit complexity. In this paper, the use of alternating logic and complemented logic are analyzed as low-cost approaches to concurrent error detection. Different architectural approaches for the neural network design are considered to march the implementation constraints.
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DFT - Efficient Time Redundancy for error correcting inner-product units and convolvers
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI, 1Co-Authors: Yuang Ming Hsu, Vincenzo Piuri, Earl E. SwartzlanderAbstract:Fault tolerance can be achieved by using Time Redundancy with modest hardware overhead at the expense of computation Time. In this paper the REcomputing with Triplication With Voting (RETWV) technique is applied to complex arithmetic units, such as inner product units and convolvers for concurrent error correction. Hardware complexity, delay, and throughput of the RETWV concurrent error correcting inner product units are analyzed and compared. It is seen that RETWV designs can be faster than the conventional design. That is, in addition to their concurrent error correcting capability, the throughput of RETWV designs is higher than that of their nonredundant counterparts. This result is significant because this shows that the RETWV technique, which is a Time Redundancy approach, can be used in high performance systems.
Ramesh Karri - One of the best experts on this subject based on the ideXlab platform.
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HOST - SLICED: Slide-based concurrent error detection technique for symmetric block ciphers
2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), 2010Co-Authors: Jeyavijayan Rajendran, Hetal Sanket Borad, Shyam Mantravadi, Ramesh KarriAbstract:Fault attacks, wherein faults are deliberately injected into cryptographic devices, can compromise their security. Moreover, in the emerging nanometer regime of VLSI, accidental faults will occur at very high rates. While straightforward hardware Redundancy based concurrent error detection (CED) can detect transient and permanent faults, it entails 100% area overhead. On the other hand, Time Redundancy based CED can only detect transient faults with minimum area overhead but entails 100% Time overhead. In this paper we present a general Time Redundancy based CED technique called SLICED for pipelined implementations of symmetric block cipher. SLICED SLIdes one encryption over another and compares their results for CED as a basis for protection against accidental faults and deliberate fault attacks.
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Concurrent error detection for involutional functions with applications in fault-tolerant cryptographic hardware design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006Co-Authors: Nikhil Joshi, J. Sundararajan, Ramesh KarriAbstract:In this paper, a Time Redundancy based Concurrent Error Detection (CED) technique targeting involutional functions is presented. A function F is an involution if F(F(x))=x. The proposed CED technique exploits the involution property and checks if x=F(F(x)). Unlike traditional Time Redundancy based CED methods, this technique can detect both permanent and transient faults
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Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002Co-Authors: Ramesh KarriAbstract:Concurrent error detection (CED) based on Time Redundancy entails performing the normal computation and the re-computation at different Times and then comparing their results. Time Redundancy implemented can only detect transient faults. We present two algorithm-level Time-Redundancy-based CED schemes that exploit register transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the Synopsys behavior complier (BC), to validate the schemes.
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Algorithm level recomputing using allocation diversity: a register transfer level approach to Time Redundancy-based concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2002Co-Authors: Ramesh KarriAbstract:In this paper, the authors propose an algorithm-level Time Redundancy-based concurrent error detection (CED) scheme against permanent and transient faults by exploiting the hardware allocation diversity at the register transfer level. Although the normal computation and the recomputation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. The authors show that the proposed scheme provides very good CED capability with very low area overhead.
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ITC - Algorithm level recomputing with allocation diversity: a register transfer level Time Redundancy based concurrent error detection technique
Proceedings International Test Conference 2001 (Cat. No.01CH37260), 1Co-Authors: Ramesh KarriAbstract:Proposes an algorithm-level Time Redundancy based CED scheme that exploits the hardware allocation diversity at the register transfer (RT) level. Although the normal computation and the re-computation are carried out on the same data path, the operation-to-operator allocation for the normal computation is different from the operation-to-operator allocation for the recomputation. We show that proposed scheme provides very good CED capability with very low area overhead.
Yuang Ming Hsu - One of the best experts on this subject based on the ideXlab platform.
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Fault Tolerant Arithmetic
The Kluwer International Series in Engineering and Computer Science, 1997Co-Authors: Yuang Ming HsuAbstract:This chapter summarizes various techniques used to achieve fault tolerance in computer arithmetic. There are basically three approaches including hardware Redundancy, information Redundancy, and Time Redundancy. Hardware Redundancy has the highest hardware overhead. However, its delay is minimal. In the information Redundancy approach, both the hardware complexity and delay are higher than other approaches. Time Redundancy uses the smallest amount of hardware at the expense of extra computation Time. In this research a concurrent error correcting technique based on Time Redundancy called Time shared TMR is developed. It has been successfully applied to ripple carry adders and array multipliers. VLSI ripple carry adders and array multipliers are designed. They are compared in area, delay and cycle Time. The Time shared TMR technique can also be applied to more complex arithmetic processors like sorting networks, FFT arrays, convolvers, and inner product units. This research is significant because the Time shared TMR technique proves to be a high reliability, low hardware complexity, and reasonable delay penalty solution to fault tolerant arithmetic.
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Time Redundancy for error detecting neural networks
Proceedings IEEE International Conference on Wafer Scale Integration (ICWSI), 1Co-Authors: Yuang Ming Hsu, Vincenzo Piuri, Earl E. SwartzlanderAbstract:Concurrent error detection at an architectural level is often a basic requirement to achieve fault tolerance in neural networks for mission-critical applications. Time Redundancy allows for concurrent error detection with low circuit complexity. In this paper, the use of alternating logic and complemented logic are analyzed as low-cost approaches to concurrent error detection. Different architectural approaches for the neural network design are considered to march the implementation constraints.
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DFT - Efficient Time Redundancy for error correcting inner-product units and convolvers
Proceedings of International Workshop on Defect and Fault Tolerance in VLSI, 1Co-Authors: Yuang Ming Hsu, Vincenzo Piuri, Earl E. SwartzlanderAbstract:Fault tolerance can be achieved by using Time Redundancy with modest hardware overhead at the expense of computation Time. In this paper the REcomputing with Triplication With Voting (RETWV) technique is applied to complex arithmetic units, such as inner product units and convolvers for concurrent error correction. Hardware complexity, delay, and throughput of the RETWV concurrent error correcting inner product units are analyzed and compared. It is seen that RETWV designs can be faster than the conventional design. That is, in addition to their concurrent error correcting capability, the throughput of RETWV designs is higher than that of their nonredundant counterparts. This result is significant because this shows that the RETWV technique, which is a Time Redundancy approach, can be used in high performance systems.
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ASAP - Recomputing by operand exchanging: a Time-Redundancy approach for fault-tolerant neural networks
Proceedings The International Conference on Application Specific Array Processors, 1Co-Authors: Yuang Ming Hsu, Earl E. Swartzlander, Vincenzo PiuriAbstract:The use of neural networks in mission-critical applications requires concurrent error detection and correction at architectural level to provide high consistency and reliability of system's outputs. Time Redundancy allows for fault tolerance in digital realizations with low circuit complexity increase. In this paper, we propose the use of REcomputation with eXchanged Operands-an approach based on operands' rotation-to introduce concurrent error detection and correction, when timing constraints are not particularly strict. Different architectural approaches for neural design are considered to match the implementation constraints and to show the versatility of the proposed solutions.
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ISCAS - Fault-tolerant neural architectures: the use of rotated operands
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 1Co-Authors: Yuang Ming Hsu, Vincenzo Piuri, Earl E. SwartzlanderAbstract:The use of neural networks in mission-critical applications requires concurrent error detection and correction at architectural level to provide high consistency and reliability of system outputs. Time Redundancy allows for fault tolerance in digital realizations with low circuit complexity increase when timing constraints are not particularly strict. The use of Time Redundancy implemented via operand rotation is discussed in this paper.
Fabrizio Lombardi - One of the best experts on this subject based on the ideXlab platform.
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Reconfiguration of two-dimensional VLSI arrays by Time-Redundancy
[1992] Proceedings International Conference on Wafer Scale Integration, 1Co-Authors: S. Yurttas, Fabrizio LombardiAbstract:The authors present various approaches for reconfiguring two-dimensional VLSI arrays using pure Time-Redundancy, i.e., no spare cells are employed. This technique is based on the full processing utilization of fault free cells. The basic principles of the proposed Time-Redundancy technique are discussed. The first approach is based on a distributed execution of the reconfiguration process. The second is based on a more complex reconfiguration procedure which accounts for an iterative execution of the first approach. These approaches have been evaluated under multiple faults in both cells and in the switches of the provided interconnection network. >
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RTSS - New approaches for the reconfiguration of two-dimensional VLSI arrays using Time-Redundancy
Proceedings. Real-Time Systems Symposium, 1Co-Authors: S. Yurttas, Fabrizio LombardiAbstract:Two novel approaches are presented in which no spare cells are used. They are based on the full processing utilization of fault-free cells by exploiting the single-product-step of a systolic array. This results in a reconfigured array with no degradation of computational speed. The basic principles of the Time-Redundancy technique are discussed, with particular emphasis on the selection and allocation processes for finding the reconfiguration-solution in real-Time. The first approach is based on a distributed execution of the reconfiguration process. The immediate advantages of this approach are its simplicity of implementation and the fast execution Time. The second approach is based on a more complex reconfiguration procedure that accounts for an iterative execution of the first approach. Appropriate conditions for its correct execution are presented. >
Alain Girault - One of the best experts on this subject based on the ideXlab platform.
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Time-Redundancy transformations for adaptive fault-tolerant circuits
2015Co-Authors: Dmitry Burlyaev, Pascal Fradet, Alain GiraultAbstract:We present a novel logic-level circuit transformation technique for the automatic insertion of fault-tolerance properties. The transformations, based on Time-Redundancy, allow dynamic changes of the level of Redundancy without interrupting the computation. The proposed concept of dynamic Time Redundancy permits adaptive circuits whose fault-tolerance properties can be “on-the-fly” traded-off for throughput. The approach is technologically independent and does not require any specific hardware support. Experimental results on the ITC'99 benchmark suite indicate that the benefits of our method grow with the combinational size of the circuit. Dynamic double and triple Time redundant transformations generate circuits 1.7 to 2.9 Times smaller than full Triple-Modular Redundancy (TMR). This transformation is a good alternative to TMR for logic-intensive safety-critical circuits where low hardware overhead or only temporary fault-tolerance guarantees are needed.
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automatic Time Redundancy transformation for fault tolerant circuits
Field Programmable Gate Arrays, 2015Co-Authors: Dmitry Burlyaev, Pascal Fradet, Alain GiraultAbstract:We present a novel logic-level circuit transformation technique for automatic insertion of fault-tolerance properties. Our transformation uses double-Time Redundancy coupled with micro-checkpointing, rollback and a speedup mode. To the best of our knowledge, our solution is the only technologically independent scheme capable to correct the multiple bit-flips caused by a Single-Event Transient (SET) with double-Time Redundancy. The approach allows soft-error masking (within the considered fault-model) and keeps the same input/output behavior regardless error occurrences. Our technique trades-off the circuit throughput for a small hardware overhead. Experimental results on the ITC'99 benchmark suite indicate that the benefits of our methods grow with the combinational size of the circuit. The hardware overhead is 2.7 to 6.1 Times smaller than full Triple Modular Redundancy (TMR) with double loss in throughput. We do not consider configuration memory corruption and our approach is readily applicable to Flash-based FPGAs. Our method does not require any specific hardware support and is an interesting alternative to TMR for logic-intensive designs.
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FPGA - Automatic Time-Redundancy Transformation for Fault-Tolerant Circuits
Proceedings of the 2015 ACM SIGDA International Symposium on Field-Programmable Gate Arrays, 2015Co-Authors: Dmitry Burlyaev, Pascal Fradet, Alain GiraultAbstract:We present a novel logic-level circuit transformation technique for automatic insertion of fault-tolerance properties. Our transformation uses double-Time Redundancy coupled with micro-checkpointing, rollback and a speedup mode. To the best of our knowledge, our solution is the only technologically independent scheme capable to correct the multiple bit-flips caused by a Single-Event Transient (SET) with double-Time Redundancy. The approach allows soft-error masking (within the considered fault-model) and keeps the same input/output behavior regardless error occurrences. Our technique trades-off the circuit throughput for a small hardware overhead. Experimental results on the ITC'99 benchmark suite indicate that the benefits of our methods grow with the combinational size of the circuit. The hardware overhead is 2.7 to 6.1 Times smaller than full Triple Modular Redundancy (TMR) with double loss in throughput. We do not consider configuration memory corruption and our approach is readily applicable to Flash-based FPGAs. Our method does not require any specific hardware support and is an interesting alternative to TMR for logic-intensive designs.
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AHS - Time-Redundancy transformations for adaptive fault-tolerant circuits
2015 NASA ESA Conference on Adaptive Hardware and Systems (AHS), 2015Co-Authors: Dmitry Burlyaev, Pascal Fradet, Alain GiraultAbstract:We present a novel logic-level circuit transformation technique for the automatic insertion of fault-tolerance properties. The transformations, based on Time-Redundancy, allow dynamic changes of the level of Redundancy without interrupting the computation. The proposed concept of dynamic Time Redundancy permits adaptive circuits whose fault-tolerance properties can be “on-the-fly” traded-off for throughput. The approach is technologically independent and does not require any specific hardware support. Experimental results on the ITC'99 benchmark suite indicate that the benefits of our method grow with the combinational size of the circuit. Dynamic double and triple Time redundant transformations generate circuits 1.7 to 2.9 Times smaller than full Triple-Modular Redundancy (TMR). This transformation is a good alternative to TMR for logic-intensive safety-critical circuits where low hardware overhead or only temporary fault-tolerance guarantees are needed.
