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Peter R. Kinget - One of the best experts on this subject based on the ideXlab platform.
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a 0 008mm 2 2 4ghz type i sub Sampling ring oscillator based Phase locked loop with a 239 7db fom and 64dbc reference spurs
Custom Integrated Circuits Conference, 2018Co-Authors: Shravan S. Nagam, Peter R. KingetAbstract:A ring-oscillator (RO) based PLL is presented combining a type-I architecture and a sub-Sampling Phase detector (SSPD). It achieves low jitter thanks to the wide-bandwidth type-I loop and low reference spurs thanks to the SSPD with its sample-and-hold function and high gain. The integrating filter capacitor is avoided, resulting in very low area. The RO PLL prototype in 65nm CMOS occupies 0.008mm2, has a loop bandwidth of 15MHz and tunes from 2 to 3.2GHz. It consumes 6.1mW at 2.4GHz with a Phase noise of −122.6dBc/Hz at 1MHz offset. The measured reference spurs, RMSjitter and FoMjitter are −64.2dBc, 422fs and −239.7dB.
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A Low-Jitter Ring-Oscillator Phase-Locked Loop Using Feedforward Noise Cancellation With a Sub-Sampling Phase Detector
IEEE Journal of Solid-State Circuits, 2018Co-Authors: Shravan S. Nagam, Peter R. KingetAbstract:Ring-oscillator (RO)-based Phase-locked loops (PLLs) are very attractive for system-on-chip applications for their compactness and tuning range, but suffer from high jitter and supply noise sensitivity. This paper presents a sub-Sampling Phase detector (SSPD)-based feedforward noise cancellation (FFNC) technique to improve these drawbacks of the RO PLL. The FFNC scheme utilizes the already available SSPD output to perform cancellation with high sensitivity while utilizing low power and area overhead. The 2- to 2.8-GHz RO PLL proof-of-principle prototype occupies 0.022 mm2 active area in 65 nm CMOS; it achieves a 633 fs rms jitter at 2.36 GHz with 5.86 mW power consumption and an figure of merit (FOMjitter) of −236.3 dB. The cancellation reduces the jitter by $1.4\times $ , the Phase noise by 10.2 dB to −123.5 dBc/Hz at 300-kHz offset, and the RO supply sensitivity by 19.5 dB for a 1 mVpp 100-kHz noise tone on the RO supply.
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a sub Sampling assisted Phase frequency detector for low noise plls with robust operation under supply interference
IEEE Transactions on Circuits and Systems, 2015Co-Authors: Karthik Tripurari, Shihan Yu, Peter R. KingetAbstract:Sub-Sampling Phase detectors (SSPDs) have recently been demonstrated to enable Phase-locked loop (PLL) realizations with very low in-band noise. However, the PLL becomes susceptible to disturbances or interference via substrate or power supply coupling as experienced in systems on chip (SOCs), which could put the PLL out of lock. A tri-state Phase-frequency detector with a dead-zone is traditionally added to act as an auxiliary frequency-locked loop (FLL) to enable the PLL to regain lock, albeit after a long delay. We propose a different solution to combine a tri-state PFD with an SSPD wherein the PLL is prevented from losing its lock while simultaneously achieving an improved in-band Phase noise performance. A 2.2 GHz integer-N PLL has been prototyped in a 65 nm CMOS process to demonstrate the advantages of the proposed combined Phase detector. It was experimentally verified that the PLL is more robust to disturbances than a PLL with a sub-Sampling Phase detector; it achieves a measured in-band Phase noise of $-$ 122 dBc/Hz when operating with the proposed combined PD from a 1.1 V supply voltage.
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CICC - A 2.2GHz PLL using a Phase-frequency detector with an auxiliary sub-Sampling Phase detector for in-band noise suppression
2011 IEEE Custom Integrated Circuits Conference (CICC), 2011Co-Authors: Chun-wei Hsu, Karthik Tripurari, Peter R. KingetAbstract:Tri-state digital Phase-frequency detectors (PFDs) are widely used for the large capture and locking range that they enable, but suffer from relatively large in-band Phase noise. Sub-Sampling Phase detectors have recently been demonstrated to offer very low in-band noise but with only a very small capture range. We show how a PFD and a sub-Sampling Phase detector can be combined to maintain the Phase-frequency detection capabilities while simultaneously obtaining in-band noise suppression. A 2.2GHz PLL is demonstrated in a 65nm CMOS process with an on-chip loop filter area of 0.04mm2. The measured in-band Phase noise improves from −110dBc/Hz to −122dBc/Hz when the auxiliary sub-Sampling Phase detector is active.
Etiënne L. M. Vermeirssen - One of the best experts on this subject based on the ideXlab platform.
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Passive sampler Phases for pesticides: evaluation of AttractSPE™ SDB-RPS and HLB versus Empore™ SDB-RPS
Environmental Science and Pollution Research, 2021Co-Authors: Benjamin Becker, Christian Kochleus, Denise Spira, Christel Möhlenkamp, Julia Bachtin, Stefan Meinecke, Etiënne L. M. VermeirssenAbstract:In this study, three different passive Sampling receiving Phases were evaluated, with a main focus on the comparability of established styrene-divinylbenzene reversed Phase sulfonated (SDB-RPS) Sampling Phase from Empore™ (E-RPS) and novel AttractSPE™ (A-RPS). Furthermore, AttractSPE™ hydrophilic-lipophilic balance (HLB) disks were tested. To support Sampling Phase selection for ongoing monitoring needs, it is important to have information on the characteristics of alternative Phases. Three sets of passive samplers (days 1–7, days 8–14, and days 1–14) were exposed to a continuously exchanged mixture of creek and rainwater in a stream channel system under controlled conditions. The system was spiked with nine pesticides in two peak scenarios, with log K _OW values ranging from approx. − 1 to 5. Three analytes were continuously spiked at a low concentration. All three Sampling Phases turned out to be suitable for the chosen analytes, and, in general, uptake rates were similar for all three materials, particularly for SDB-RPS Phases. Exceptions concerned bentazon, where E-RPS sampled less than 20% compared with the other Phases, and nicosulfuron, where HLB sampled noticeably more than both SDB-RPS Phases. All three Phases will work for environmental monitoring. They are very similar, but differences indicate one cannot just use literature calibration data and transfer these from one SDB Phase to another, though for most compounds, it may work fine. Graphical abstract
Bram Nauta - One of the best experts on this subject based on the ideXlab platform.
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a 2 4 ghz 16 Phase sub Sampling fractional n pll with robust soft loop switching
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Dongyi Liao, Bram Nauta, Fa Foster Dai, Eric A.m. KlumperinkAbstract:A 16-modulo fractional-N sub-Sampling Phase-locked loop (SSPLL) with a quadrature voltage-controlled oscillator (VCO) interpolating 16 output Phases is presented in this paper. Automatic soft switching between the sub-Sampling Phase control loop and the frequency control loop is proposed to improve loop robustness against perturbations and interferences, achieving more stable loop dynamics for a larger range of Phase errors compared with prior art SSPLL designs. A capacitive Phase interpolation network is implemented for 16-Phase clock generation starting from quadrature Phases. The 16 Phases are further utilized to achieve fractional-N operation with a sub-Sampling Phase detector. This passive Phase interpolation at the VCO frequency introduces no extra noise or power and avoids in-band Phase noise degradation for fractional-N mode. Implemented in a 130-nm CMOS technology, the SSPLL chip achieves a measured in-band Phase noise of −120 dBc/Hz and a measured integrated jitter of 158 fs at 2.4 GHz, while consuming 21 mW with 16 output Phases. The measured reference spur and fractional spur levels are −72 and −52 dBc, respectively.
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Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018Co-Authors: Bart J. Thijssen, Eric A.m. Klumperink, Philip Quinlan, Bram NautaAbstract:This brief presents a feedforward Phase noise cancellation technique to reduce Phase noise of the output clock signal of a Phase-locked loop (PLL). It uses a sub-Sampling Phase detector to measure the Phase noise and a variable time delay for cancellation. Both Phase noise and spurs are reduced. Analytical expressions have been derived that characterize the performance of this technique and show its fundamental limitations. A sub-Sampling PLL with the cancellation technique as a built-in feature is described. The feedforward technique has no stability requirements in contrast to conventional PLL architectures. The Phase noise reduction bandwidth is increased to almost a third of the reference frequency—3x the maximal bandwidth for 3rd order type-II PLLs. The proposed analytical model shows a Phase noise reduction of 9 dB at a frequency offset of $ {{f_{\text {ref}}/10}}$ . The total rms jitter is improved by 7.2 dB. The analytical results are verified by simulations.
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spur reduction techniques for Phase locked loops exploiting a sub Sampling Phase detector
IEEE Journal of Solid-state Circuits, 2010Co-Authors: Xiang Gao, Eric A.m. Klumperink, Gerard G. Socci, Mounir Bohsali, Bram NautaAbstract:This paper presents Phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-Sampling Phase detector (SSPD) (which is also referred to as a Sampling Phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the Sampling at the reference frequency. The underlying VCO Sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is <; -80 dBc. The PLL consumes 3.8 mW while the in-band Phase noise is -121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3psrms.
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spur reduction techniques for plls using sub Sampling Phase detection
International Solid-State Circuits Conference, 2010Co-Authors: Xiang Gao, Eric A.m. Klumperink, Gerard G. Socci, Mounir Bohsali, Bram NautaAbstract:In PLL designs, a wide loop bandwidth is often desired as it offers fast settling time, reduces on-chip loop filter area and sensitivity of the VCO to pulling. The reference spur is a major issue when the bandwidth is increased, because ripples on the VCO control line undergo less filtering by the loop filter. This paper proposes design techniques based on sub-Sampling Phase detection to reduce the reference spur of a 2.2GHz PLL to −80dBc at a high loop-bandwidth-to-reference-frequency ratio (f BW /f ref ) of 1/20.
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Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector
IEEE Journal of Solid-State Circuits, 2010Co-Authors: Xiang Gao, Eric A.m. Klumperink, Gerard G. Socci, Mounir Bohsali, Bram NautaAbstract:This paper presents Phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-Sampling Phase detector (SSPD) (which is also referred to as a Sampling Phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the Sampling at the reference frequency. The underlying VCO Sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is
Eric A.m. Klumperink - One of the best experts on this subject based on the ideXlab platform.
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a 2 4 ghz 16 Phase sub Sampling fractional n pll with robust soft loop switching
IEEE Journal of Solid-state Circuits, 2018Co-Authors: Dongyi Liao, Bram Nauta, Fa Foster Dai, Eric A.m. KlumperinkAbstract:A 16-modulo fractional-N sub-Sampling Phase-locked loop (SSPLL) with a quadrature voltage-controlled oscillator (VCO) interpolating 16 output Phases is presented in this paper. Automatic soft switching between the sub-Sampling Phase control loop and the frequency control loop is proposed to improve loop robustness against perturbations and interferences, achieving more stable loop dynamics for a larger range of Phase errors compared with prior art SSPLL designs. A capacitive Phase interpolation network is implemented for 16-Phase clock generation starting from quadrature Phases. The 16 Phases are further utilized to achieve fractional-N operation with a sub-Sampling Phase detector. This passive Phase interpolation at the VCO frequency introduces no extra noise or power and avoids in-band Phase noise degradation for fractional-N mode. Implemented in a 130-nm CMOS technology, the SSPLL chip achieves a measured in-band Phase noise of −120 dBc/Hz and a measured integrated jitter of 158 fs at 2.4 GHz, while consuming 21 mW with 16 output Phases. The measured reference spur and fractional spur levels are −72 and −52 dBc, respectively.
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Feedforward Phase Noise Cancellation Exploiting a Sub-Sampling Phase Detector
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018Co-Authors: Bart J. Thijssen, Eric A.m. Klumperink, Philip Quinlan, Bram NautaAbstract:This brief presents a feedforward Phase noise cancellation technique to reduce Phase noise of the output clock signal of a Phase-locked loop (PLL). It uses a sub-Sampling Phase detector to measure the Phase noise and a variable time delay for cancellation. Both Phase noise and spurs are reduced. Analytical expressions have been derived that characterize the performance of this technique and show its fundamental limitations. A sub-Sampling PLL with the cancellation technique as a built-in feature is described. The feedforward technique has no stability requirements in contrast to conventional PLL architectures. The Phase noise reduction bandwidth is increased to almost a third of the reference frequency—3x the maximal bandwidth for 3rd order type-II PLLs. The proposed analytical model shows a Phase noise reduction of 9 dB at a frequency offset of $ {{f_{\text {ref}}/10}}$ . The total rms jitter is improved by 7.2 dB. The analytical results are verified by simulations.
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spur reduction techniques for Phase locked loops exploiting a sub Sampling Phase detector
IEEE Journal of Solid-state Circuits, 2010Co-Authors: Xiang Gao, Eric A.m. Klumperink, Gerard G. Socci, Mounir Bohsali, Bram NautaAbstract:This paper presents Phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-Sampling Phase detector (SSPD) (which is also referred to as a Sampling Phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the Sampling at the reference frequency. The underlying VCO Sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is <; -80 dBc. The PLL consumes 3.8 mW while the in-band Phase noise is -121 dBc/Hz at 200 kHz and the output jitter integrated from 10 kHz to 100 MHz is 0.3psrms.
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spur reduction techniques for plls using sub Sampling Phase detection
International Solid-State Circuits Conference, 2010Co-Authors: Xiang Gao, Eric A.m. Klumperink, Gerard G. Socci, Mounir Bohsali, Bram NautaAbstract:In PLL designs, a wide loop bandwidth is often desired as it offers fast settling time, reduces on-chip loop filter area and sensitivity of the VCO to pulling. The reference spur is a major issue when the bandwidth is increased, because ripples on the VCO control line undergo less filtering by the loop filter. This paper proposes design techniques based on sub-Sampling Phase detection to reduce the reference spur of a 2.2GHz PLL to −80dBc at a high loop-bandwidth-to-reference-frequency ratio (f BW /f ref ) of 1/20.
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Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector
IEEE Journal of Solid-State Circuits, 2010Co-Authors: Xiang Gao, Eric A.m. Klumperink, Gerard G. Socci, Mounir Bohsali, Bram NautaAbstract:This paper presents Phase-locked loop (PLL) reference-spur reduction design techniques exploiting a sub-Sampling Phase detector (SSPD) (which is also referred to as a Sampling Phase detector). The VCO is sampled by the reference clock without using a frequency divider and an amplitude controlled charge pump is used which is inherently insensitive to mismatch. The main remaining source of the VCO reference spur is the periodic disturbance of the VCO by the Sampling at the reference frequency. The underlying VCO Sampling spur mechanisms are analyzed and their effect is minimized by using dummy samplers and isolation buffers. A duty-cycle-controlled reference buffer and delay-locked loop (DLL) tuning are proposed to further reduce the worst case spur level. To demonstrate the effectiveness of the proposed spur reduction techniques, a 2.21 GHz PLL is designed and fabricated in 0.18 μm CMOS technology. While using a high loop-bandwidth-to-reference-frequency ratio of 1/20, the reference spur measured from 20 chips is
John E. Bowers - One of the best experts on this subject based on the ideXlab platform.
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linear coherent receiver based on a broadband and Sampling optical Phase locked loop
International Topical Meeting on Microwave Photonics, 2007Co-Authors: John E. Bowers, Darko Zibar, Anand Ramaswamy, L A Johansson, Jonathan Klamkin, M N Sysak, L A Coldren, M J W Rodwell, L Lembo, R YoshimitsuAbstract:A novel coherent receiver for linear optical Phase demodulation is proposed and experimentally demonstrated. The receiver, based on a broadband optical Phase-lock loop has a bandwidth of 1.45 GHz. Using the receiver in an analog link experiment, a spurious free dynamic range of 125 dBHz2/3 is measured at 300 MHz. Further, theoretical investigations are presented demonstrating receiver operation at high frequencies (>2 GHz) using a Sampling Phase-locked loop.
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novel optical Phase demodulator based on a Sampling Phase locked loop
IEEE Photonics Technology Letters, 2007Co-Authors: Darko Zibar, Leif A. Johansson, Hsu-feng Chou, Anand Ramaswamy, Mark J. W. Rodwell, John E. BowersAbstract:A novel Phase-locked coherent demodulator, based on a Sampling Phase-locked loop, is presented and investigated theoretically. The demodulator is capable of operating at high frequencies, by using optical Sampling to downconvert the high-frequency input radio-frequency signal to the frequency range of the baseband loop. We develop a detailed theoretical model of the (Sampling) Phase-locked coherent demodulator and perform detailed numerical simulations. The simulation results show that the operation of the Sampling demodulator resembles the operation of the baseband demodulator for very short optical pulses (<2 ps). Furthermore, we investigate how the signal-to-noise ratio of the demodulator is affected by timing and amplitude jitter of the pulsed optical source
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Novel Optical Phase Demodulator Based on a Sampling Phase-Locked Loop
IEEE Photonics Technology Letters, 2007Co-Authors: Darko Zibar, Leif A. Johansson, Hsu-feng Chou, Anand Ramaswamy, Mark J. W. Rodwell, John E. BowersAbstract:A novel Phase-locked coherent demodulator, based on a Sampling Phase-locked loop, is presented and investigated theoretically. The demodulator is capable of operating at high frequencies, by using optical Sampling to downconvert the high-frequency input radio-frequency signal to the frequency range of the baseband loop. We develop a detailed theoretical model of the (Sampling) Phase-locked coherent demodulator and perform detailed numerical simulations. The simulation results show that the operation of the Sampling demodulator resembles the operation of the baseband demodulator for very short optical pulses (
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Investigation of a Novel Optical Phase Demodulator Based on a Sampling Phase-Locked Loop
2006 International Topical Meeting on Microwave Photonics, 2006Co-Authors: Darko Zibar, Leif A. Johansson, Hsu-feng Chou, Anand Ramaswamy, Mark J. W. Rodwell, John E. BowersAbstract:A novel Phase-locked coherent demodulator, based on a Sampling Phase-locked loop, is presented and investigated theoretically. The demodulator is capable of operating at high-frequencies, by using optical Sampling to downconvert the high-frequency input RF signal to the frequency range of the baseband loop. We develop a detailed theoretical model of the (Sampling) Phase-locked coherent demodulator and perform detailed numerical simulations. The simulation results show that the operation of the Sampling demodulator resembles the operation of the baseband demodulator for very short optical pulses (
