The Experts below are selected from a list of 219 Experts worldwide ranked by ideXlab platform

A.g. Andreou - One of the best experts on this subject based on the ideXlab platform.

  • Surface micromachining in Silicon on Sapphire CMOS technology
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: F. Tejada, A.g. Andreou, D.k. Wickenden, A.s. Francomacaro
    Abstract:

    We report on the design and fabrication of surface micromachined microelectromechanical structures (MEMS) in an ultra thin Silicon (UTSi) on Sapphire CMOS process [Peregrine Semiconductor (PE) Silicon on Sapphire (SOS) process]. This is the first demonstration of surface micromachined MEMS structures in a CMOS process fabricated on a Sapphire substrate.

  • ISCAS (4) - Surface micromachining in Silicon on Sapphire CMOS technology
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: F. Tejada, A.g. Andreou, D.k. Wickenden, A.s. Francomacaro
    Abstract:

    We report on the design and fabrication of surface micromachined microelectromechanical structures (MEMS) in an ultra thin Silicon (UTSi) on Sapphire CMOS process [Peregrine Semiconductor (PE) Silicon on Sapphire (SOS) process]. This is the first demonstration of surface micromachined MEMS structures in a CMOS process fabricated on a Sapphire substrate.

  • 5 mv gbit s Silicon on Sapphire cmos optical receiver
    Electronics Letters, 2001
    Co-Authors: A. Apsel, A.g. Andreou
    Abstract:

    A low power, Gbit/s optical receiver for inter-chip communication is described. The receiver is fabricated in 0.5 /spl mu/m Silicon on Sapphire CMOS. Results of operation with power consumption of 5 mW are presented.

  • Silicon on Sapphire cmos for optoelectronic microsystems
    IEEE Circuits and Systems Magazine, 2001
    Co-Authors: A.g. Andreou, Z K Kalayjian, Alyssa B Apsel, Philippe O Pouliquen, Ravindra A Athale, G Simonis, R Reedy
    Abstract:

    we report on a hybrid integration approach that represents a paradigm shift from traditional optoelectronic integration and packaging methods. A recent metamorphosis and wider availability of Silicon on Sapphire CMOS VLSI technology is generating a great deal of excitement in the optoelectronic systems community as it offers simple and elegant solutions to the many system integration and packaging challenges that one faces when employing bulk Silicon CMOS technologies. In the bulk Silicon CMOS processes that are used for high-speed interface electronics the substrate is absorbing at both 850 nm and 980 nm wavelengths, necessitating complex and expensive integration procedures such as VCSEL substrate removal to enable the implementation of optical vias through the substrate. Working together, the optical transparency of the Sapphire substrate, its superb thermal conductivity and the excellent high speed device characteristics of Silicon-on-Sapphire CMOS circuits make this technology an excellent choice for cost effective optoelectronic Die-AS-Package (DASP) systems and for implementing optical interconnects for high performance computer architectures. What is perhaps even more important, packaging and input/output interface issues can now be addressed at the CMOS wafer fabrication level where input/output structures can be accurately defined, optimized and processed using lithographic techniques, eliminating problematic die post-processing and packaging-related optical alignment issues.

A.s. Francomacaro - One of the best experts on this subject based on the ideXlab platform.

  • Surface micromachining in Silicon on Sapphire CMOS technology
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: F. Tejada, A.g. Andreou, D.k. Wickenden, A.s. Francomacaro
    Abstract:

    We report on the design and fabrication of surface micromachined microelectromechanical structures (MEMS) in an ultra thin Silicon (UTSi) on Sapphire CMOS process [Peregrine Semiconductor (PE) Silicon on Sapphire (SOS) process]. This is the first demonstration of surface micromachined MEMS structures in a CMOS process fabricated on a Sapphire substrate.

  • ISCAS (4) - Surface micromachining in Silicon on Sapphire CMOS technology
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: F. Tejada, A.g. Andreou, D.k. Wickenden, A.s. Francomacaro
    Abstract:

    We report on the design and fabrication of surface micromachined microelectromechanical structures (MEMS) in an ultra thin Silicon (UTSi) on Sapphire CMOS process [Peregrine Semiconductor (PE) Silicon on Sapphire (SOS) process]. This is the first demonstration of surface micromachined MEMS structures in a CMOS process fabricated on a Sapphire substrate.

A.g. Andreou - One of the best experts on this subject based on the ideXlab platform.

  • Photo-battery fabricated in Silicon on Sapphire CMOS
    Electronics Letters, 2008
    Co-Authors: M.a. Marwick, A.g. Andreou
    Abstract:

    A report is presented on the design and characterisation of an energy harvesting circuit fabricated in Silicon on Sapphire CMOS technology. The insulating Sapphire substrate permits the connection of multiple photodiodes in series to obtain a higher output voltage, and its optical transparency allows for backside illumination. The conversion efficiency of the photo-battery is measured at greater than 1% for wavelengths ranging from infrared to ultraviolet. An active Silicon area of 1 cm2 at 50001x ambient illumination yields approximately 60 muW of power.

  • Digital isolation amplifier in Silicon-on-Sapphire CMOS
    Electronics Letters, 2007
    Co-Authors: E. Culurciello, P.o. Pouliquen, A.g. Andreou
    Abstract:

    The design and fabrication results of a monolithic four-channel digital isolation amplifier in a 0.5 mum Silicon-on-Sapphire technology is reported. The isolation device is manufactured in a single die, taking advantage of the isolation properties of the Sapphire substrate. The individual isolation channels can operate in excess of 40 Mbit/s using digital phase-shift-keying modulation. Modulation of the input signal is used to increase immunity to errors at low input data rates. The device can tolerate ground bounces of 1 V/mus and isolate more than 800 V

  • 3D integrated sensors in Silicon-on-Sapphire CMOS
    2006 IEEE International Symposium on Circuits and Systems, 2006
    Co-Authors: E. Culurciello, A.g. Andreou
    Abstract:

    We fabricated a 3D-integrated multi-chip sensor and actuator and demonstrated the ability of communication with a floating die and no galvanic connection. The prototype was fabricated on a conventional 0.5mum Silicon-on-Sapphire (SOS) process. We designed a heater and a temperature sensor module with digital output based on a bandgap voltage reference. We used capacitive coupling to provide both intra-die communication of the digital temperature readings and also energy-harvesting by means of a charge pump. The non-galvanically interconnected prototype is an enabling technology for three-dimensional VLSI fabrication, 3D CMOS, wafer stacking and packaging

  • 5 mV, Gbit/s Silicon on Sapphire CMOS optical receiver
    Electronics Letters, 2001
    Co-Authors: A. Apsel, A.g. Andreou
    Abstract:

    A low power, Gbit/s optical receiver for inter-chip communication is described. The receiver is fabricated in 0.5 /spl mu/m Silicon on Sapphire CMOS. Results of operation with power consumption of 5 mW are presented.

Eugenio Culurciello - One of the best experts on this subject based on the ideXlab platform.

  • Silicon-on-Sapphire Circuits and Systems
    2009
    Co-Authors: Eugenio Culurciello
    Abstract:

    The Latest Silicon-on-Sapphire CMOS Design and Fabrication Techniques Develop high-performance SOS-based microsystems. Filled with examples, schematics, and charts, Silicon-on-Sapphire Circuits and Systems covers the latest analog and mixed-signal IC design techniques. Learn how to assemble SOI/SOS circuits and systems, work with an insulated substrate and device models, create miniaturized amplifiers and switches, and build ADCs and DACs. You will also find information on constructing photosensitive circuits and memory chips, deploying integrated biosensors, overcoming noise and power issues, and maximizing efficiency. Discover how to: Extract active and passive device models and parameters Design single-stage amplifiers, op amps, references, and comparators Build digital processors, data converters, and mixed-mode circuits Deploy photodetectors in active pixel sensor and imaging arrays Optimize performance, quantum efficiency, and signal-to-noise ratio Develop current and voltage mode SOS-based biosensors Use CMOS, monolithic, and digital phase-shift isolation techniques Integrate the latest three-dimensional assemblies and die packages Table of contents Ch1. The Silicon-on-Sapphire Fabrication Process Ch2. SoS Device Modeling for Circuit Design Ch3. SoS Amplifiers and Basic Analog Circuits Ch4. SoS Linear Analog Circuits Ch5. SoS Digital Circuits Ch6. SoS Analog to Digital Conversion Systems Ch7. SoS Image Sensors and optoelectronic Systems Ch8. SoS Biosensor System Interfaces Ch9. SoS Advanced Analog Circuits and Systems Ch10. SoS Communication Circuits and Systems

  • Ultralow Current Measurements With Silicon-on-Sapphire Integrator Circuits
    IEEE Electron Device Letters, 2009
    Co-Authors: Eugenio Culurciello, Hazael Montanaro
    Abstract:

    This letter reports the results on measurements and modeling of the ultralow current measurement capability of a Silicon-on-Sapphire current integrator circuit. We have tested the lowest possible current measurable with the device and the noise performance with picoampere input currents. The device is capable of resolving subpicoampere currents with an rms noise of 350 fA in a 110-Hz bandwidth. The device is also capable of digitally measuring currents up to 100 muA by employing a pulse-based A/D converters.

  • Phototransistor image sensor in Silicon on Sapphire
    2008 IEEE International Symposium on Circuits and Systems, 2008
    Co-Authors: Joon Hyuk Park, Eugenio Culurciello
    Abstract:

    We present a back-illuminated 32 x 32 pixel image sensor in 0.5-mum Silicon-on-Sapphire process. The imager performs "snap-shot" image acquisition and analog readout at a continuous rate of thousands of frames/s and consumes as little as 250 muW. Each pixel consists of a phototransistor and a memory capacitor in 40 mum x 40 mum with a fill factor of 43%. The image sensor is suited for hyper-spectral imaging at high speeds.

  • Back-illuminated ultraviolet image sensor in Silicon-on-Sapphire
    2008 IEEE International Symposium on Circuits and Systems, 2008
    Co-Authors: Joon Hyuk Park, Eugenio Culurciello
    Abstract:

    We present a back-illuminated 32 x 32 pixel SOI image sensor chip in 0.5-mum Silicon-on-Sapphire process capable of ultraviolet imaging. The imager performs "snap-shot" image acquisition and analog readout at a continuous rate of a thousand frames/s and consumes as little as 650 muW. Each pixel consists of a photodiode and a memory capacitor in 40 mum x 40 mum with a fill factor of 43%. The image sensor is suited for hyper-spectral imaging at high speeds.

  • ISCAS - Phototransistor image sensor in Silicon on Sapphire
    2008 IEEE International Symposium on Circuits and Systems, 2008
    Co-Authors: Joon Hyuk Park, Eugenio Culurciello
    Abstract:

    We present a back-illuminated 32 x 32 pixel image sensor in 0.5-mum Silicon-on-Sapphire process. The imager performs "snap-shot" image acquisition and analog readout at a continuous rate of thousands of frames/s and consumes as little as 250 muW. Each pixel consists of a phototransistor and a memory capacitor in 40 mum x 40 mum with a fill factor of 43%. The image sensor is suited for hyper-spectral imaging at high speeds.

F. Tejada - One of the best experts on this subject based on the ideXlab platform.

  • Surface micromachining in Silicon on Sapphire CMOS technology
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: F. Tejada, A.g. Andreou, D.k. Wickenden, A.s. Francomacaro
    Abstract:

    We report on the design and fabrication of surface micromachined microelectromechanical structures (MEMS) in an ultra thin Silicon (UTSi) on Sapphire CMOS process [Peregrine Semiconductor (PE) Silicon on Sapphire (SOS) process]. This is the first demonstration of surface micromachined MEMS structures in a CMOS process fabricated on a Sapphire substrate.

  • ISCAS (4) - Surface micromachining in Silicon on Sapphire CMOS technology
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004
    Co-Authors: F. Tejada, A.g. Andreou, D.k. Wickenden, A.s. Francomacaro
    Abstract:

    We report on the design and fabrication of surface micromachined microelectromechanical structures (MEMS) in an ultra thin Silicon (UTSi) on Sapphire CMOS process [Peregrine Semiconductor (PE) Silicon on Sapphire (SOS) process]. This is the first demonstration of surface micromachined MEMS structures in a CMOS process fabricated on a Sapphire substrate.