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E. Fujiwara - One of the best experts on this subject based on the ideXlab platform.

  • a class of random multiple bits in a Byte error correcting and Single Byte error detecting s sub t b ec s sub b ed codes
    IEEE Transactions on Computers, 2003
    Co-Authors: G. Umanesan, E. Fujiwara
    Abstract:

    Correcting multiple random bit errors that corrupt a Single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft, and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. On the other hand, entire chip failures are often presumed to be less likely events and, in most applications, detection of errors caused by Single chip failures are preferred to correction due to check bit length considerations. Under this situation, codes capable of correcting random multiple bit errors that are confined to a Single chip output and simultaneously detecting errors caused by Single chip failures are attractive for application in high speed memory systems. This paper proposes a class of codes called Single t/b-error Correcting-Single b-bit Byte Error Detecting (S/sub t/b/EC-S/sub b/ED) codes which have the capability of correcting random t-bit errors occurring within a Single b-bit Byte and simultaneously indicating Single b-bit Byte errors. For the practical case where the chip data output is 8 bits, i.e., b = 8, the S/sub 3/8/EC-S/sub 8/ED code proposed in this paper, for example, requires only 12 check bits at information length 64 bits. Furthermore, this S/sub 3/8/EC-S/sub 8/ED code is capable of correcting errors caused by Single subarray data faults, i.e., Single 4-bit Byte errors, as well. This paper also shows that perfect S/sub (b-t)/b/EC-S/sub b/ED codes, i.e., perfect S/sub t/b/EC-S/sub b/ED codes for the case where t = b - 1, do exist and provides a theorem to construct these codes.

  • a class of random multiple bits within a Byte error correcting codes with Single Byte error detecting capability for memory systems
    International Symposium on Information Theory, 2002
    Co-Authors: G. Umanesan, E. Fujiwara
    Abstract:

    We propose a class of codes called Single t-bits within a b-bit Byte error correcting-Single b-bit Byte error detecting (S/sub t/b/EC-S/sub b/ED) code for high speed semiconductor memory systems.

  • Single Byte error control codes with adjacent double bit error correcting capability for computer memory systems
    Proceedings. 2001 IEEE International Symposium on Information Theory (IEEE Cat. No.01CH37252), 2001
    Co-Authors: G. Umanesan, E. Fujiwara
    Abstract:

    We propose a class of codes called adjacent double bit error correcting-Single Byte error detecting (ADEC-S/sub b/ED) codes for high speed semiconductor memory systems.

  • Single Byte error control codes with double bit within a block error correcting capability for semiconductor memory systems
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2000
    Co-Authors: G. Umanesan, E. Fujiwara
    Abstract:

    Computer memory systems when exposed to strong electromagnetic waves or radiation are highly vulnerable to multiple random bit errors. Under this situation, we cannot apply existing SEC-DED or S/sub b/EC capable codes because they provide insufficient error control performance. This correspondence considers the situation where two random bits in a memory chip are corrupted by strong electromagnetic waves or radioactive particles and proposes two classes of codes that are capable of correcting random double bit errors occurring within a chip. The proposed codes, called Double bit within a block Error Correcting-Single Byte Error Detecting ((DEC)/sub B/-S/sub b/ED) code and Double bit within a block Error Correcting-Single Byte Error Correcting ((DEC)/sub B/-S/sub b/EC) code, are suitable for recent computer memory systems.

  • Single b bit Byte error correcting and double bit error detecting codes for high speed memory systems
    IEEE International Symposium on Fault-Tolerant Computing, 1992
    Co-Authors: E. Fujiwara, M Hamada
    Abstract:

    The authors propose a novel design method for Single b-bit Byte error correcting and double bit error detecting code, called Sb EC-DED code, suitable for high-speed memory systems using Byte organized RAM chips. This type of Byte error control code is practical from the viewpoint of having less redundancy and stronger error control capability than the existing codes. A code design method using elements from a coset of a subfield under addition gives the practical Sb EC-DED code with 64 information bits and 4-bit Byte length which has the same check-bit length, 12 bits, as that of the Single Byte error correcting code. This also has very high error detection capabilities of random double Byte errors and of random triple bit errors. >

G. Umanesan - One of the best experts on this subject based on the ideXlab platform.

  • a class of random multiple bits in a Byte error correcting and Single Byte error detecting s sub t b ec s sub b ed codes
    IEEE Transactions on Computers, 2003
    Co-Authors: G. Umanesan, E. Fujiwara
    Abstract:

    Correcting multiple random bit errors that corrupt a Single DRAM chip becomes very important in certain applications, such as semiconductor memories used in computer and communication systems, mobile systems, aircraft, and satellites. This is because, in these applications, the presence of strong electromagnetic waves in the environment or the bombardment of an energetic particle on a DRAM chip is highly likely to upset more than just one bit stored in that chip. On the other hand, entire chip failures are often presumed to be less likely events and, in most applications, detection of errors caused by Single chip failures are preferred to correction due to check bit length considerations. Under this situation, codes capable of correcting random multiple bit errors that are confined to a Single chip output and simultaneously detecting errors caused by Single chip failures are attractive for application in high speed memory systems. This paper proposes a class of codes called Single t/b-error Correcting-Single b-bit Byte Error Detecting (S/sub t/b/EC-S/sub b/ED) codes which have the capability of correcting random t-bit errors occurring within a Single b-bit Byte and simultaneously indicating Single b-bit Byte errors. For the practical case where the chip data output is 8 bits, i.e., b = 8, the S/sub 3/8/EC-S/sub 8/ED code proposed in this paper, for example, requires only 12 check bits at information length 64 bits. Furthermore, this S/sub 3/8/EC-S/sub 8/ED code is capable of correcting errors caused by Single subarray data faults, i.e., Single 4-bit Byte errors, as well. This paper also shows that perfect S/sub (b-t)/b/EC-S/sub b/ED codes, i.e., perfect S/sub t/b/EC-S/sub b/ED codes for the case where t = b - 1, do exist and provides a theorem to construct these codes.

  • a class of random multiple bits within a Byte error correcting codes with Single Byte error detecting capability for memory systems
    International Symposium on Information Theory, 2002
    Co-Authors: G. Umanesan, E. Fujiwara
    Abstract:

    We propose a class of codes called Single t-bits within a b-bit Byte error correcting-Single b-bit Byte error detecting (S/sub t/b/EC-S/sub b/ED) code for high speed semiconductor memory systems.

  • Single Byte error control codes with adjacent double bit error correcting capability for computer memory systems
    Proceedings. 2001 IEEE International Symposium on Information Theory (IEEE Cat. No.01CH37252), 2001
    Co-Authors: G. Umanesan, E. Fujiwara
    Abstract:

    We propose a class of codes called adjacent double bit error correcting-Single Byte error detecting (ADEC-S/sub b/ED) codes for high speed semiconductor memory systems.

  • Single Byte error control codes with double bit within a block error correcting capability for semiconductor memory systems
    Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2000
    Co-Authors: G. Umanesan, E. Fujiwara
    Abstract:

    Computer memory systems when exposed to strong electromagnetic waves or radiation are highly vulnerable to multiple random bit errors. Under this situation, we cannot apply existing SEC-DED or S/sub b/EC capable codes because they provide insufficient error control performance. This correspondence considers the situation where two random bits in a memory chip are corrupted by strong electromagnetic waves or radioactive particles and proposes two classes of codes that are capable of correcting random double bit errors occurring within a chip. The proposed codes, called Double bit within a block Error Correcting-Single Byte Error Detecting ((DEC)/sub B/-S/sub b/ED) code and Double bit within a block Error Correcting-Single Byte Error Correcting ((DEC)/sub B/-S/sub b/EC) code, are suitable for recent computer memory systems.

Cristina Silvano - One of the best experts on this subject based on the ideXlab platform.

  • Construction techniques for systematic SEC-DED codes with Single Byte error detection and partial correction capability for computer memory systems
    IEEE Transactions on Information Theory, 1995
    Co-Authors: L. Penzo, Donatella Sciuto, Cristina Silvano
    Abstract:

    Three new techniques are proposed for constructing a class of codes that extends the protection provided by previous Single error correcting (SEC)-double error detecting (DED)-Single Byte error detecting (SBD) codes. The proposed codes are systematic odd-weight-column SEC-DED-SBD codes providing also the correction of any odd number of erroneous bits per Byte, where a Byte represents a cluster of b bits of the codeword that are fed by the same memory chip or card. These codes are useful for practical applications to enhance the reliability and the data integrity of Byte-organized computer memory systems against transient, intermittent, and permanent failures. In particular they represent a good tradeoff between the overhead in terms of additional check bits and the reliability improvement, due to the capability to correct at least 50% of the multiple errors per Byte.

L. Penzo - One of the best experts on this subject based on the ideXlab platform.

  • Construction techniques for systematic SEC-DED codes with Single Byte error detection and partial correction capability for computer memory systems
    IEEE Transactions on Information Theory, 1995
    Co-Authors: L. Penzo, Donatella Sciuto, Cristina Silvano
    Abstract:

    Three new techniques are proposed for constructing a class of codes that extends the protection provided by previous Single error correcting (SEC)-double error detecting (DED)-Single Byte error detecting (SBD) codes. The proposed codes are systematic odd-weight-column SEC-DED-SBD codes providing also the correction of any odd number of erroneous bits per Byte, where a Byte represents a cluster of b bits of the codeword that are fed by the same memory chip or card. These codes are useful for practical applications to enhance the reliability and the data integrity of Byte-organized computer memory systems against transient, intermittent, and permanent failures. In particular they represent a good tradeoff between the overhead in terms of additional check bits and the reliability improvement, due to the capability to correct at least 50% of the multiple errors per Byte.

Donatella Sciuto - One of the best experts on this subject based on the ideXlab platform.

  • Construction techniques for systematic SEC-DED codes with Single Byte error detection and partial correction capability for computer memory systems
    IEEE Transactions on Information Theory, 1995
    Co-Authors: L. Penzo, Donatella Sciuto, Cristina Silvano
    Abstract:

    Three new techniques are proposed for constructing a class of codes that extends the protection provided by previous Single error correcting (SEC)-double error detecting (DED)-Single Byte error detecting (SBD) codes. The proposed codes are systematic odd-weight-column SEC-DED-SBD codes providing also the correction of any odd number of erroneous bits per Byte, where a Byte represents a cluster of b bits of the codeword that are fed by the same memory chip or card. These codes are useful for practical applications to enhance the reliability and the data integrity of Byte-organized computer memory systems against transient, intermittent, and permanent failures. In particular they represent a good tradeoff between the overhead in terms of additional check bits and the reliability improvement, due to the capability to correct at least 50% of the multiple errors per Byte.