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Neil M. Zimmerman - One of the best experts on this subject based on the ideXlab platform.

  • effect of device design on charge offset drift in si sio2 Single Electron Devices
    Journal of Applied Physics, 2018
    Co-Authors: Erick Ochoa, Neil M. Zimmerman, Daniel Sanchez, Justin K Perron, M D Stewart
    Abstract:

    We have measured the low-frequency time instability known as charge offset drift of Si/SiO 2 Single Electron Devices (SEDs) with and without an overall poly-Si top gate. We find that SEDs with a poly-Si top gate have significantly less charge offset drift, exhibiting fewer isolated jumps and a factor of two reduction in fluctuations about a stable mean value. The observed reduction can be accounted for by the electrostatic reduction in the mutual capacitance C m between defects and the quantum dot and increase in the total defect capacitance C d due to the top gate. These results depart from the prominent interpretation that the level of charge offset drift in SEDs is determined by the intrinsic material properties, forcing consideration of the device design as well. We expect these results to be of importance in developing SEDs for applications from quantum information to metrology or wherever charge noise or integrability of Devices is a challenge.

  • stability of Single Electron Devices charge offset drift
    Applied Sciences, 2016
    Co-Authors: M D Stewart, Neil M. Zimmerman
    Abstract:

    Single Electron Devices (SEDs) afford the opportunity to isolate and manipulate individual Electrons. This ability imbues SEDs with potential applications in a wide array of areas from metrology (current and capacitance) to quantum information. Success in each application ultimately requires exceptional performance, uniformity, and stability from SEDs which is currently unavailable. In this review, we discuss a time instability of SEDs that occurs at low frequency ( ≪ 1 Hz) called charge offset drift. We review experimental work which shows that charge offset drift is large in metal-based SEDs and absent in Si-SiO2-based Devices. We discuss the experimental results in the context of glassy relaxation as well as prospects of SED device applications.

  • charge offset stability in si Single Electron Devices with al gates
    arXiv: Mesoscale and Nanoscale Physics, 2014
    Co-Authors: Neil M. Zimmerman, C H Yang, Nai Shyan Lai, W H Lim, A S Dzurak
    Abstract:

    We report on the charge offset drift (time stability) in Si Single Electron Devices (SEDs) defined with aluminum (Al) gates. The size of the charge offset drift (0.15 $e$) is intermediate between that of Al/AlO$_x$/Al tunnel junctions (greater than 1 $e$) and Si SEDs defined with Si gates (0.01 $e$). This range of values suggests that defects in the AlO$_x$ are the main cause of the charge offset drift instability.

  • Fabrication and Electrical Characterization of Fully CMOS-Compatible Si Single-Electron Devices
    IEEE Transactions on Electron Devices, 2013
    Co-Authors: P. J. Koppinen, Michael Stewart, Neil M. Zimmerman
    Abstract:

    We present electrical data of silicon Single-Electron Devices fabricated with CMOS techniques and protocols. The easily tuned Devices show clean Coulomb diamonds at T = 30mK and a charge offset drift of 0.01e over eight days. In addition, the Devices exhibit robust transistor characteristics, including uniformity within about ±0.25 V in the threshold voltage, gate resistances greater than 10 GΩ, and immunity to dielectric breakdown in electric fields as high as 4 MV/cm. These results highlight the benefits in device performance of a silicon-foundry-compatible process for Single-Electron device fabrication.

  • fabrication and electrical characterization of fully cmos si Single Electron Devices
    arXiv: Mesoscale and Nanoscale Physics, 2012
    Co-Authors: P. J. Koppinen, M D Stewart, Neil M. Zimmerman
    Abstract:

    We present electrical data of silicon Single Electron Devices fabricated with CMOS techniques and protocols. The easily tuned Devices show clean Coulomb diamonds at T = 30 mK and charge offset drift of 0.01 e over eight days. In addition, the Devices exhibit robust transistor characteristics including uniformity within about 0.5 V in the threshold voltage, gate resistances greater than 10 G{\Omega}, and immunity to dielectric breakdown in electric fields as high as 4 MV/cm. These results highlight the benefits in device performance of a fully CMOS process for Single Electron device fabrication.

Yasuo Takahashi - One of the best experts on this subject based on the ideXlab platform.

  • charge offset stability of Single Electron Devices based on Single layered fe nanodot array
    AIP Advances, 2021
    Co-Authors: Takayuki Gyakushi, Yuki Asai, Atsushi Tsurumakifukuchi, Masashi Arita, Shusaku Honjo, Yasuo Takahashi
    Abstract:

    In metal-based Single-Electron Devices (SEDs), charge-offset drift has been observed, which is a time-dependent instability caused by charge noise. This instability is an issue in the application of new information processing Devices, such as neural network Devices, quantum computing Devices (charge sensing), and reservoir computing Devices. Therefore, the charge-offset drift in metal-based SEDs needs to be suppressed. However, the charge-offset stability of metal-based SEDs has not been investigated in depth, except in the case of Al and Al2O3 SEDs. In this work, Fe-based SEDs formed by Single-layer Fe nanodot arrays embedded in MgF2 were studied with regard to their charge-offset stability. Using Devices that produce simple current oscillations, the charge-offset drift (ΔQ0) of Fe-based SEDs was evaluated by focusing on peak shifts of the simple current oscillation over time, despite the use of a multi-dot system. This drift (ΔQ0 ≈ 0.3e) was shown to be much lower than in SEDs with Al-dots and Al2O3 tunnel junctions. Notably, the charge-offset drift in the metal-based SEDs was suppressed using the Fe–MgF2 system. The excellent stability of these Devices was attributed to the material properties of the Fe–MgF2 system. Finally, as the Fe nanodot array contained numerous dots, the effect of satellite dots acting as traps on the charge-offset instability was discussed. The findings of this study will be important in future applications of metal-based SEDs in new information processing Devices.

  • double gate Single Electron Devices formed by Single layered fe nanodot array
    IEEE Silicon Nanoelectronics Workshop, 2020
    Co-Authors: Takayuki Gyakushi, Yuki Asai, Beommo Byun, Ikuma Amano, Atsushi Tsurumakifukuchi, Masashi Arita, Yasuo Takahashi
    Abstract:

    Single-Electron Devices (SEDs) composed of nanometer-scale dots have been attracted due to their low-power consumption and high functionality. In this paper, we fabricated double-gate SEDs formed by Fe nanodot array which showed periodic Coulomb blockade oscillation characteristics derived from a Single dot. As a result, we confirmed that the charge state of the Single dot could be controlled by two gates. In addition, we also found an interesting phenomenon that the two gates, which attached parallel to the nanodot array, unevenly affected the nanodots.

  • Silicon Single-Electron Devices
    Nanostructure Science and Technology, 2009
    Co-Authors: Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, Hiroshi Inokawa
    Abstract:

    Single-Electron Devices (SEDs) are attracting a lot of attention because of their ability to manipulate just one Electron. They operate using a Coulomb blockade, which occurs in tiny structures made of conductive material due to electrostatic interactions between confined Electrons. Although any kind of conductive material can be used, silicon is preferable in terms of integrated circuit applications because, on a silicon substrate, SEDs can be used in combination with conventional complementary metal-oxide-semiconductor (CMOS) circuits. In addition, the well-established technologies used for fabricating CMOS large-scale integrated circuits can be employed to make these small structures. Silicon SEDs are employed in two fields: memory and logic. The simple operating principle of SEDs, i.e., capacitive coupling, has meant that many kinds of logic and memory applications have been proposed and tested. Another important issue with SEDs is the accurate control of a Single Electron, which is a challenge that must be met by ultimate Electronics. The current status of silicon-based SEDs is introduced.

  • silicon Single Electron Devices and their applications
    International Symposium on Multiple-Valued Logic, 2000
    Co-Authors: Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, Katsumi Murase
    Abstract:

    We have developed two novel methods of fabricating very small Si Single-Electron transistors (SETs), called PAttern-Dependent OXidation (PADOX) and Vertical PAttern-Dependent OXidation (V-PADOX). These methods exploit special phenomena that occur when small Si structures on SiO/sub 2/ are thermally oxidized. Since the size of the resultant Si island of the SET is about 10 nm, we can observe the conductance oscillations in the SET even at room temperature. The controllability and reproducibility of these methods are excellent because of the stability of the thermal oxidation process. We are using PADOX and V-PADOX to integrate Single-Electron Devices (SEDs)for sophisticated functions. We have fabricated and tested several kinds of memory and logic Devices, This paper also describes applications of multi-input gate SETs to multiple-valued logic circuits.

  • silicon Single Electron Devices
    International Journal of Electronics, 1999
    Co-Authors: Yasuo Takahashi, Akira Fujiwara, Masao Nagase, Hideo Namatsu, Kenji Kurihara, Kazumi Iwadate, Katsumi Murase
    Abstract:

    Silicon Single-Electron transistors (SETs) were fabricated by using very flat silicon-on-insulator (SOI) substrates, high resolution Electron beam (EB) lithography and etching techniques. In addition, we developed a special fabrication method called pattern-dependent oxidation with which a one-dimensional Si wire can be converted into a small Si island with a tunnelling barrier at each end. Since the Si island is around 10 nm, we could observe the conductance oscillation in the SET even at room temperature. The controllability and reproducibility of this method were confirmed through analysing the effects of size on electrical characteristics. We were also able to observe Single-Electron memory effects by using these novel techniques.

A S Dzurak - One of the best experts on this subject based on the ideXlab platform.

  • charge offset stability in si Single Electron Devices with al gates
    arXiv: Mesoscale and Nanoscale Physics, 2014
    Co-Authors: Neil M. Zimmerman, C H Yang, Nai Shyan Lai, W H Lim, A S Dzurak
    Abstract:

    We report on the charge offset drift (time stability) in Si Single Electron Devices (SEDs) defined with aluminum (Al) gates. The size of the charge offset drift (0.15 $e$) is intermediate between that of Al/AlO$_x$/Al tunnel junctions (greater than 1 $e$) and Si SEDs defined with Si gates (0.01 $e$). This range of values suggests that defects in the AlO$_x$ are the main cause of the charge offset drift instability.

  • scaling of ion implanted si p Single Electron Devices
    Nanotechnology, 2007
    Co-Authors: C C Escott, F E Hudson, V Chan, K D Petersson, R G Clark, A S Dzurak
    Abstract:

    We present a modelling study on the scaling prospects for phosphorus in silicon (Si:P) Single Electron Devices using readily available commercial and free-to-use software. The Devices comprise phosphorus ion implanted, metallically doped (n+) dots (size range 50?500?nm) with source and drain reservoirs. Modelling results are compared to measurements on fabricated Devices and discussed in the context of scaling down to few-Electron structures. Given current fabrication constraints, we find that Devices with 70?75 donors per dot should be realizable. We comment on methods for further reducing this number.

M D Stewart - One of the best experts on this subject based on the ideXlab platform.

  • effect of device design on charge offset drift in si sio2 Single Electron Devices
    Journal of Applied Physics, 2018
    Co-Authors: Erick Ochoa, Neil M. Zimmerman, Daniel Sanchez, Justin K Perron, M D Stewart
    Abstract:

    We have measured the low-frequency time instability known as charge offset drift of Si/SiO 2 Single Electron Devices (SEDs) with and without an overall poly-Si top gate. We find that SEDs with a poly-Si top gate have significantly less charge offset drift, exhibiting fewer isolated jumps and a factor of two reduction in fluctuations about a stable mean value. The observed reduction can be accounted for by the electrostatic reduction in the mutual capacitance C m between defects and the quantum dot and increase in the total defect capacitance C d due to the top gate. These results depart from the prominent interpretation that the level of charge offset drift in SEDs is determined by the intrinsic material properties, forcing consideration of the device design as well. We expect these results to be of importance in developing SEDs for applications from quantum information to metrology or wherever charge noise or integrability of Devices is a challenge.

  • stability of Single Electron Devices charge offset drift
    Applied Sciences, 2016
    Co-Authors: M D Stewart, Neil M. Zimmerman
    Abstract:

    Single Electron Devices (SEDs) afford the opportunity to isolate and manipulate individual Electrons. This ability imbues SEDs with potential applications in a wide array of areas from metrology (current and capacitance) to quantum information. Success in each application ultimately requires exceptional performance, uniformity, and stability from SEDs which is currently unavailable. In this review, we discuss a time instability of SEDs that occurs at low frequency ( ≪ 1 Hz) called charge offset drift. We review experimental work which shows that charge offset drift is large in metal-based SEDs and absent in Si-SiO2-based Devices. We discuss the experimental results in the context of glassy relaxation as well as prospects of SED device applications.

  • fabrication and electrical characterization of fully cmos si Single Electron Devices
    arXiv: Mesoscale and Nanoscale Physics, 2012
    Co-Authors: P. J. Koppinen, M D Stewart, Neil M. Zimmerman
    Abstract:

    We present electrical data of silicon Single Electron Devices fabricated with CMOS techniques and protocols. The easily tuned Devices show clean Coulomb diamonds at T = 30 mK and charge offset drift of 0.01 e over eight days. In addition, the Devices exhibit robust transistor characteristics including uniformity within about 0.5 V in the threshold voltage, gate resistances greater than 10 G{\Omega}, and immunity to dielectric breakdown in electric fields as high as 4 MV/cm. These results highlight the benefits in device performance of a fully CMOS process for Single Electron device fabrication.

Katsumi Murase - One of the best experts on this subject based on the ideXlab platform.

  • silicon Single Electron Devices and their applications
    International Symposium on Multiple-Valued Logic, 2000
    Co-Authors: Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, Katsumi Murase
    Abstract:

    We have developed two novel methods of fabricating very small Si Single-Electron transistors (SETs), called PAttern-Dependent OXidation (PADOX) and Vertical PAttern-Dependent OXidation (V-PADOX). These methods exploit special phenomena that occur when small Si structures on SiO/sub 2/ are thermally oxidized. Since the size of the resultant Si island of the SET is about 10 nm, we can observe the conductance oscillations in the SET even at room temperature. The controllability and reproducibility of these methods are excellent because of the stability of the thermal oxidation process. We are using PADOX and V-PADOX to integrate Single-Electron Devices (SEDs)for sophisticated functions. We have fabricated and tested several kinds of memory and logic Devices, This paper also describes applications of multi-input gate SETs to multiple-valued logic circuits.

  • silicon Single Electron Devices
    International Journal of Electronics, 1999
    Co-Authors: Yasuo Takahashi, Akira Fujiwara, Masao Nagase, Hideo Namatsu, Kenji Kurihara, Kazumi Iwadate, Katsumi Murase
    Abstract:

    Silicon Single-Electron transistors (SETs) were fabricated by using very flat silicon-on-insulator (SOI) substrates, high resolution Electron beam (EB) lithography and etching techniques. In addition, we developed a special fabrication method called pattern-dependent oxidation with which a one-dimensional Si wire can be converted into a small Si island with a tunnelling barrier at each end. Since the Si island is around 10 nm, we could observe the conductance oscillation in the SET even at room temperature. The controllability and reproducibility of this method were confirmed through analysing the effects of size on electrical characteristics. We were also able to observe Single-Electron memory effects by using these novel techniques.

  • double island Single Electron Devices a useful unit device for Single Electron logic lsi s
    IEEE Transactions on Electron Devices, 1999
    Co-Authors: Akira Fujiwara, Yasuo Takahashi, Masao Nagase, Hideo Namatsu, Kenji Kurihara, Kenji Yamazaki, Katsumi Murase
    Abstract:

    We fabricated a Single-Electron device that is useful as a unit device for Single-Electron logic circuits. The device is a three-current-terminal device fabricated on a silicon-on-insulator (SOI) wafer, which includes two Si islands whose electric potential can be controlled by gates. Sub-50-nm Si islands were integrated in an area smaller than 0.02 /spl mu/m/sup 2/ through self-aligned formation of the islands by pattern-dependent oxidation (PADOX) of a T-shaped wire. By PADOX, each island was embedded in one branch of the T-shaped wire. We show two electrical characteristics which demonstrate the usefulness of this device as a circuit element. First, current switching between two branches was performed at 30 K by using gate voltage to control the Coulomb blockade in each island. Second, a correlation between the two currents was observed because the two islands were integrated close to each other. The latter indicates a capacitive coupling between the islands, which opens up the possibility of one-by-one transfer of Electrons in this device. These findings show that the proposed island-integration technique is applicable to making ultra-low-power and highly integrated Single-Electron circuits.