The Experts below are selected from a list of 35946 Experts worldwide ranked by ideXlab platform
Ming-dou Ker - One of the best experts on this subject based on the ideXlab platform.
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pmos based power rail esd clamp circuit with adjustable holding voltage controlled by esd detection circuit
Electrical Overstress Electrostatic Discharge Symposium, 2011Co-Authors: Chihting Yeh, Yungchih Liang, Ming-dou KerAbstract:A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.
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investigation and design of on chip power rail esd clamp circuits without suffering latchup like failure during system level esd test
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Ming-dou Ker, Chengcheng YenAbstract:On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-mum CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a ldquolatch-onrdquo state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.
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SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-/spl mu/m fully salicided CMOS process
IEEE Transactions on Electron Devices, 2004Co-Authors: Ming-dou Ker, Zi-ping ChenAbstract:A dynamic-holding-voltage silicon-controlled rectifier (DHVSCR) device is proposed and verified in a 0.25-/spl mu/m/2.5-V salicided CMOS process. In the DHVSCR device structure, the control nMOS and pMOS transistors are directly embedded in SCR device structure. The proposed DHVSCR device has the characteristics of tunable holding voltage and holding current by changing the gate voltage of embedded nMOS and pMOS. Under normal circuit operating condition, the DHVSCR has a holding voltage higher than the supply voltage without causing a latch-up issue. Under an electrostatic discharge (ESD) stress condition, the DHVSCR has a lower holding voltage to effectively clamp the overshooting ESD voltage. From the experimental results, the DHVSCR with a device width of 50 /spl mu/m can sustain a human-body-model ESD level of 5.6 kV.
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Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143), 1Co-Authors: Ming-dou Ker, Hun-hsien ChangAbstract:A novel design has been proposed to safely apply the NCLSCR (NMOS-controlled lateral SCR) and PCLSCR (PMOS-controlled lateral SCR) devices for whole-chip ESD (electrostatic discharge) protection in CMOS ICs without causing the unexpected operation errors or the VDD-to-VSS latchup issue. By using the cascode configuration, the ESD protection circuit with the cascode NCLSCRs or PCLSCRs has a tunable holding voltage greater than VDD of the ICs. Such cascode NCLSCRs (or PCLSCRs) can provide the CMOS IC's with effective ESD protection but without accidentally triggering on by the overshooting (under-shooting) noise pulses in the system applications. This novel cascode NCLSCRs (PCLSCRs) design has been practically applied to protect the ICs in a 0.35 /spl mu/m silicide CMOS technology with the HBM ESD robustness above 3 kV.
Chengcheng Yen - One of the best experts on this subject based on the ideXlab platform.
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investigation and design of on chip power rail esd clamp circuits without suffering latchup like failure during system level esd test
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Ming-dou Ker, Chengcheng YenAbstract:On-chip power-rail electrostatic discharge (ESD) protection circuit designed with active ESD detection function is the key role to significantly improve ESD robustness of CMOS integrated circuits (ICs). Four power-rail ESD clamp circuits with different ESD-transient detection circuits were fabricated in a 0.18-mum CMOS process and tested to compare their system-level ESD susceptibility, which are named as power-rail ESD clamp circuits with typical RC-based detection, PMOS feedback, NMOS+PMOS feedback, and cascaded PMOS feedback in this work. During the system-level ESD test, where the ICs in a system have been powered up, the feedback loop used in the power-rail ESD clamp circuits provides the lock function to keep the ESD-clamping NMOS in a ldquolatch-onrdquo state. The latch-on ESD-clamping NMOS, which is often drawn with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. A modified power-rail ESD clamp circuit is proposed to solve this problem. The proposed power-rail ESD clamp circuit can provide high enough chip-level ESD robustness, and without suffering the latchup-like failure during the system-level ESD test.
Shinji Odanaka - One of the best experts on this subject based on the ideXlab platform.
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a 0 05 spl mu m cmos with ultra shallow source drain junctions fabricated by 5 kev ion implantation and rapid thermal annealing
International Electron Devices Meeting, 1994Co-Authors: A. Hori, H. Nakaoka, H. Umimoto, Kyoji Yamashita, M. Takase, N. Shimizu, B. Mizuno, Shinji OdanakaAbstract:A 0.05 /spl mu/m-PMOSFET has been fabricated for the first time, together with a 0.05 /spl mu/m-NMOSFET. For this process, ultra shallow source/drain junctions were developed on the basis of 5 keV ion implantation technology and rapid thermal annealing. The short channel effect was suppressed and Gm max reaches 460 mS/mm for NMOS and 380 mS/mm for PMOS. The delay time per stage of unloaded CMOS inverter is 13.1 psec at the supply voltage of 1.5 V. >
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A 0.05 /spl mu/m-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing
Proceedings of 1994 IEEE International Electron Devices Meeting, 1Co-Authors: A. Hori, H. Nakaoka, H. Umimoto, Kyoji Yamashita, M. Takase, N. Shimizu, B. Mizuno, Shinji OdanakaAbstract:A 0.05 /spl mu/m-PMOSFET has been fabricated for the first time, together with a 0.05 /spl mu/m-NMOSFET. For this process, ultra shallow source/drain junctions were developed on the basis of 5 keV ion implantation technology and rapid thermal annealing. The short channel effect was suppressed and Gm max reaches 460 mS/mm for NMOS and 380 mS/mm for PMOS. The delay time per stage of unloaded CMOS inverter is 13.1 psec at the supply voltage of 1.5 V. >
A. Hori - One of the best experts on this subject based on the ideXlab platform.
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a 0 05 spl mu m cmos with ultra shallow source drain junctions fabricated by 5 kev ion implantation and rapid thermal annealing
International Electron Devices Meeting, 1994Co-Authors: A. Hori, H. Nakaoka, H. Umimoto, Kyoji Yamashita, M. Takase, N. Shimizu, B. Mizuno, Shinji OdanakaAbstract:A 0.05 /spl mu/m-PMOSFET has been fabricated for the first time, together with a 0.05 /spl mu/m-NMOSFET. For this process, ultra shallow source/drain junctions were developed on the basis of 5 keV ion implantation technology and rapid thermal annealing. The short channel effect was suppressed and Gm max reaches 460 mS/mm for NMOS and 380 mS/mm for PMOS. The delay time per stage of unloaded CMOS inverter is 13.1 psec at the supply voltage of 1.5 V. >
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A 0.05 /spl mu/m-CMOS with ultra shallow source/drain junctions fabricated by 5 keV ion implantation and rapid thermal annealing
Proceedings of 1994 IEEE International Electron Devices Meeting, 1Co-Authors: A. Hori, H. Nakaoka, H. Umimoto, Kyoji Yamashita, M. Takase, N. Shimizu, B. Mizuno, Shinji OdanakaAbstract:A 0.05 /spl mu/m-PMOSFET has been fabricated for the first time, together with a 0.05 /spl mu/m-NMOSFET. For this process, ultra shallow source/drain junctions were developed on the basis of 5 keV ion implantation technology and rapid thermal annealing. The short channel effect was suppressed and Gm max reaches 460 mS/mm for NMOS and 380 mS/mm for PMOS. The delay time per stage of unloaded CMOS inverter is 13.1 psec at the supply voltage of 1.5 V. >
Prateek Jain - One of the best experts on this subject based on the ideXlab platform.
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Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration
Journal of Circuits Systems and Computers, 2018Co-Authors: Prateek Jain, Amit JoshiAbstract:An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.
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Full-Wave Bridge Rectifier with CMOS Pass Transistors Configuration
Journal of Circuits Systems and Computers, 2017Co-Authors: Prateek Jain, Amit Krishna JoshiAbstract:An effortless, more efficient full-wave bridge rectifier is introduced with minimum distortion. Efficient and exploratory combinations of CMOS logic are not only utilized to design full-wave bridge rectifier, but also as pass transistors configurations at the input. The particular CMOS logic (used to design core rectifier circuit) is a collective form of SDG-NMOS and SGS-PMOS. SDG-NMOS refers to a shorted drain gate n-channel metal oxide semiconductor. SGS-PMOS refers to shorted gate to source p-channel metal oxide semiconductor. Due to the utilization of renovated MOS configuration after the replacement of the diode, the efficiency of the full-wave bridge rectifier is increased up to 11% compared to p-n junction diode based full wave bridge rectifier. The proposed full wave bridge rectifier is a comparably low power circuit. The proposed CMOS based full-wave bridge rectifier is optimized at 45-nm CMOS technology. Cadence experimental simulation and implementations of the leakage power and efficiency demo...
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An Innovative Design: MOS Based Full-Wave Centre-Tapped Rectifier
Wireless Personal Communications, 2016Co-Authors: Prateek Jain, Shyam AkasheAbstract:A novel, more competent, low leakage and comparatively high speed full-wave centre-tapped rectifier is introduced with minimum distortion. Proficient and exploratory combinations of PMOS–PMOS or NMOS–NMOS logic are utilized to design full-wave centre-tapped rectifier. The scrupulous PMOS–PMOS logic with augmented stacked NMOS transistor is communal form of two PMOS and one NMOS transistor. The main motive of manipulating these circuits is to maintain the substrate biasing during circuit operation. The substrate biasing refers the exploitation in which substrate and drain/source terminal of a transistor is kept in reverse biasing mode. Due to utilization of modified MOS structure after replacing of diode, efficiency of full-wave centre-tapped rectifier is increased up to 20 % with compare to p-n junction diode based full wave centre-tapped rectifier and leakage power dissipation is reduced up to 57 %. The proposed circuit is designed to utilize the body effect properly to reduce the total leakage power of the circuit. The novelty of proposed circuit is the uniqueness of combination of MOS. Due to this; the proposed circuit has impressive resultant parameter with compare to other circuits and previous results. Proposed MOS based full-wave centre-tapped rectifier is optimized at 45 nm CMOS technology and cadence simulation experimental implementations of the leakage power and efficiency demonstrate better consistency through the proposed circuit.
