The Experts below are selected from a list of 324 Experts worldwide ranked by ideXlab platform
Rui P. Martins - One of the best experts on this subject based on the ideXlab platform.
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A 0.0045-mm2 32.4-μW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation
2016Co-Authors: Zushu Yan, Pui-in Mak, Man-kay Law, Wei Wang, Student Member, Senior Member, Rui P. MartinsAbstract:Abstract—This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact micropower two-Stage Amplifier for wide capacitive load (CL) drivability. It features: 1) a valuable left half-plane zero to enhance the closed-loop stability over a wide range of CL; 2) no extra bias circuit and power, as the CM is embedded into the first Stage of the Amplifier, and 3) only one very small (subpicofarad) compensation capacitor improving the transient settling and area efficiency. Detailed analytical treatments of the Amplifier offer the critical insights for device sizing and optimization. Fabricated in 0.18-μm CMOS, the Amplifier measures 3.06-MHz unity-gain frequency (UGF), 1.76-V/μs average slew rate (SR), and 74◦ phase margin (PM) at 20-pF CL, and 0.22-MHz UGF, 0.049-V/μs SR, and 59.8 ◦ PM at 15-nF CL. The die size is 0.0045 mm2, and power is 32.4 μW at 1.2 V. Competitive large- and small-signal figures of merit are achieved with respect to the state of the art. Index Terms—Capacitive load, capacitor multiplier (CM), CMOS, frequency compensation, stability, two-Stage Amplifier. I
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nested current mirror rail to rail output single Stage Amplifier with enhancements of dc gain gbw and slew rate
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Rui P. Martins, F MalobertiAbstract:For better area and power efficiencies, rail-to-rail-output single-Stage Amplifiers are a potential replacement of their multi-Stage counterparts, especially for display applications that entail massive buffer Amplifiers in their column drivers. This paper describes a nested-current-mirror (NCM) technique for a single-Stage Amplifier to achieve substantial enhancements of DC gain, gain-bandwidth product (GBW) and slew rate (SR). Specifically, NCM is customizable for different mirror steps, and sub mirror ratios, to balance the performance metrics and capacitive-load ( ${\rm C}_{\rm L}$ ) drivability, avoiding any compensation passives while preserving a rail-to-rail output swing. Analytical treatments of the NCM technique in terms of performance limits and robustness reveal that the NCM Amplifier can surpass the fundamental power-efficiency limit set by the basic differential-pair (DP) Amplifier. Two prototypes, 3-step and 4-step NCM Amplifiers, were fabricated in 0.18 $\mu$ m CMOS for systematic comparison with the DP Amplifier. The former represents a robust design exhibiting 72 dB DC gain and 0.0028–0.27 MHz GBW over 0.15–15 nF ${\rm C}_{\rm L}$ with $> $ 80 $^{\circ}$ phase margin (PM). The latter embodies an aggressive design attaining 84 dB DC gain and 0.013–1.24 MHz GBW over 0.15–15 nF ${\rm C}_{\rm L}$ with $> $ 62 $^{\circ}$ PM. All Amplifiers were sized for the same area (0.0013 mm $_{2}$ ) and power (3.6 $\mu$ W).
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0 0045 mm2 15 8 µw three Stage Amplifier driving 10 wide 0 15 1 5 nf capacitive loads with 50 phase margin
Electronics Letters, 2015Co-Authors: Zushu Yan, Pui-in Mak, Man-kay Law, Rui P. MartinsAbstract:A three-Stage Amplifier employing embedded capacitor-multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF-range capacitive loads (C L) is presented. Unlike the conventional current-buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain–bandwidth product. The created left-half-plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area-consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi-path G m-boosting second Stage enhances the effective transconductance and DC gain. With 0.0045 mm2 of area and 15.8 µW of power, the 0.18 µm CMOS three-Stage Amplifier measures 1.13 MHz unity-gain frequency, 0.41 V/µs average slew rate and 56.2° PM at 1 nF C L. Stable responses with >50° PM are attained for a 10 × range of C L from 0.15 to 1.5 nF. The achieved figure-of-merit accounting for both die area and power compares favourably with the state of the art.
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a 0 0045 hbox mm 2 32 4 mu hbox w two Stage Amplifier for pf to nf load using cm frequency compensation
IEEE Transactions on Circuits and Systems Ii-express Briefs, 2015Co-Authors: Wei Wang, Rui P. MartinsAbstract:This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact micropower two-Stage Amplifier for wide capacitive load ( $C_{L} $ ) drivability. It features: 1) a valuable left half-plane zero to enhance the closed-loop stability over a wide range of $C_{L} $ ; 2) no extra bias circuit and power, as the CM is embedded into the first Stage of the Amplifier, and 3) only one very small (subpicofarad) compensation capacitor improving the transient settling and area efficiency. Detailed analytical treatments of the Amplifier offer the critical insights for device sizing and optimization. Fabricated in 0.18- $\mu\hbox{m} $ CMOS, the Amplifier measures 3.06-MHz unity-gain frequency (UGF), 1.76- $\hbox{V}/\mu\hbox{s}$ average slew rate (SR), and $74^{\circ}$ phase margin (PM) at 20-pF $C_{L}$ , and 0.22-MHz UGF, 0.049- $\hbox{V}/\mu\hbox{s}$ SR, and $59.8^{\circ}$ PM at 15-nF $C_{L}$ . The die size is 0.0045 $\hbox{mm}^{2}$ , and power is $32.4\ \mu\hbox{W} $ at 1.2 V. Competitive large- and small-signal figures of merit are achieved with respect to the state of the art.
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0.0045 mm2 15.8 µW three-Stage Amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin
Electronics Letters, 2015Co-Authors: Zushu Yan, Pui-in Mak, Man-kay Law, Rui P. MartinsAbstract:A three-Stage Amplifier employing embedded capacitor-multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF-range capacitive loads (C L) is presented. Unlike the conventional current-buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain–bandwidth product. The created left-half-plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area-consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi-path G m-boosting second Stage enhances the effective transconductance and DC gain. With 0.0045 mm2 of area and 15.8 µW of power, the 0.18 µm CMOS three-Stage Amplifier measures 1.13 MHz unity-gain frequency, 0.41 V/µs average slew rate and 56.2° PM at 1 nF C L. Stable responses with >50° PM are attained for a 10 × range of C L from 0.15 to 1.5 nF. The achieved figure-of-merit accounting for both die area and power compares favourably with the state of the art.
Gyuhyeong Cho - One of the best experts on this subject based on the ideXlab platform.
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7 4μw ultra high slew rate pseudo single Stage Amplifier driving 0 1 to 15nf capacitive load with 69 phase margin
Symposium on VLSI Circuits, 2015Co-Authors: Sung-wan Hong, Gyuhyeong ChoAbstract:To achieve ultra-high slew-rate with stable operation under wide capacitive load range, pseudo single-Stage Amplifier is proposed in this paper. The proposed Amplifier achieves widest capacitive load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to state-of-the-art works. This chip was fabricated using a 0.18 μm CMOS process with area of 0.0021 mm2.
Sung-wan Hong - One of the best experts on this subject based on the ideXlab platform.
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VLSIC - 7.4μW Ultra-high slew-rate pseudo single-Stage Amplifier driving 0.1-to-15nF capacitive load with >69° phase margin
2015 Symposium on VLSI Circuits (VLSI Circuits), 2015Co-Authors: Sung-wan HongAbstract:To achieve ultra-high slew-rate with stable operation under wide capacitive load range, pseudo single-Stage Amplifier is proposed in this paper. The proposed Amplifier achieves widest capacitive load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to state-of-the-art works. This chip was fabricated using a 0.18 μm CMOS process with area of 0.0021 mm2.
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7 4μw ultra high slew rate pseudo single Stage Amplifier driving 0 1 to 15nf capacitive load with 69 phase margin
Symposium on VLSI Circuits, 2015Co-Authors: Sung-wan Hong, Gyuhyeong ChoAbstract:To achieve ultra-high slew-rate with stable operation under wide capacitive load range, pseudo single-Stage Amplifier is proposed in this paper. The proposed Amplifier achieves widest capacitive load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to state-of-the-art works. This chip was fabricated using a 0.18 μm CMOS process with area of 0.0021 mm2.
Akira Matsuzawa - One of the best experts on this subject based on the ideXlab platform.
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a 64μs start up 26 40mhz crystal oscillator with negative resistance boosting technique using reconfigurable multi Stage Amplifier
Symposium on VLSI Circuits, 2018Co-Authors: Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira MatsuzawaAbstract:This paper presents a low-energy and quick start-up 26/40 MHz crystal oscillator for IoT wireless communications. The negative resistance is boosted to reduce the start-up time by using a reconfigurable multi-Stage Amplifier during the start-up period. A variable feedforward path implemented in the multi Stage Amplifier can overcome a conventional limitation of the negative resistance. At 40 MHz oscillation, the proposed crystal oscillator fabricated in 65 nm CMOS demonstrates a start-up energy and time of 37.2 nJ and 64 μs, respectively.
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VLSI Circuits - A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier
2018 IEEE Symposium on VLSI Circuits, 2018Co-Authors: Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira MatsuzawaAbstract:This paper presents a low-energy and quick start-up 26/40 MHz crystal oscillator for IoT wireless communications. The negative resistance is boosted to reduce the start-up time by using a reconfigurable multi-Stage Amplifier during the start-up period. A variable feedforward path implemented in the multi Stage Amplifier can overcome a conventional limitation of the negative resistance. At 40 MHz oscillation, the proposed crystal oscillator fabricated in 65 nm CMOS demonstrates a start-up energy and time of 37.2 nJ and 64 μs, respectively.
Zushu Yan - One of the best experts on this subject based on the ideXlab platform.
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A 0.0045-mm2 32.4-μW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation
2016Co-Authors: Zushu Yan, Pui-in Mak, Man-kay Law, Wei Wang, Student Member, Senior Member, Rui P. MartinsAbstract:Abstract—This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact micropower two-Stage Amplifier for wide capacitive load (CL) drivability. It features: 1) a valuable left half-plane zero to enhance the closed-loop stability over a wide range of CL; 2) no extra bias circuit and power, as the CM is embedded into the first Stage of the Amplifier, and 3) only one very small (subpicofarad) compensation capacitor improving the transient settling and area efficiency. Detailed analytical treatments of the Amplifier offer the critical insights for device sizing and optimization. Fabricated in 0.18-μm CMOS, the Amplifier measures 3.06-MHz unity-gain frequency (UGF), 1.76-V/μs average slew rate (SR), and 74◦ phase margin (PM) at 20-pF CL, and 0.22-MHz UGF, 0.049-V/μs SR, and 59.8 ◦ PM at 15-nF CL. The die size is 0.0045 mm2, and power is 32.4 μW at 1.2 V. Competitive large- and small-signal figures of merit are achieved with respect to the state of the art. Index Terms—Capacitive load, capacitor multiplier (CM), CMOS, frequency compensation, stability, two-Stage Amplifier. I
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0 0045 mm2 15 8 µw three Stage Amplifier driving 10 wide 0 15 1 5 nf capacitive loads with 50 phase margin
Electronics Letters, 2015Co-Authors: Zushu Yan, Pui-in Mak, Man-kay Law, Rui P. MartinsAbstract:A three-Stage Amplifier employing embedded capacitor-multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF-range capacitive loads (C L) is presented. Unlike the conventional current-buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain–bandwidth product. The created left-half-plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area-consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi-path G m-boosting second Stage enhances the effective transconductance and DC gain. With 0.0045 mm2 of area and 15.8 µW of power, the 0.18 µm CMOS three-Stage Amplifier measures 1.13 MHz unity-gain frequency, 0.41 V/µs average slew rate and 56.2° PM at 1 nF C L. Stable responses with >50° PM are attained for a 10 × range of C L from 0.15 to 1.5 nF. The achieved figure-of-merit accounting for both die area and power compares favourably with the state of the art.
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0.0045 mm2 15.8 µW three-Stage Amplifier driving 10×-wide (0.15–1.5 nF) capacitive loads with >50° phase margin
Electronics Letters, 2015Co-Authors: Zushu Yan, Pui-in Mak, Man-kay Law, Rui P. MartinsAbstract:A three-Stage Amplifier employing embedded capacitor-multiplier compensation (ECMC) and active parallel compensation (APC) to enhance the area efficiency when driving nF-range capacitive loads (C L) is presented. Unlike the conventional current-buffer Miller compensation, ECMC applied to the dominant compensation path saves substantial power and area, while securing a large gain–bandwidth product. The created left-half-plane zero also benefits the phase margin (PM). For the APC, unlike the traditional passive parallel compensation, this work benefits from the Miller effect to avoid the area-consuming resistor, and reduces the entailed capacitances without lowering the parasitic pole position. A multi-path G m-boosting second Stage enhances the effective transconductance and DC gain. With 0.0045 mm2 of area and 15.8 µW of power, the 0.18 µm CMOS three-Stage Amplifier measures 1.13 MHz unity-gain frequency, 0.41 V/µs average slew rate and 56.2° PM at 1 nF C L. Stable responses with >50° PM are attained for a 10 × range of C L from 0.15 to 1.5 nF. The achieved figure-of-merit accounting for both die area and power compares favourably with the state of the art.
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17 2 a 0 0013mm 2 3 6μw nested current mirror single Stage Amplifier driving 0 15 to 15nf capacitive loads with 62 phase margin
International Solid-State Circuits Conference, 2014Co-Authors: Zushu Yan, Pui-in Mak, Man-kay Law, Rui P. Martins, Franco MalobertiAbstract:This paper introduces a nested-current-mirror (NCM) single-Stage Amplifier to advance its GBW-to-power/area efficiency and CL drivability beyond the multi-Stage designs, while preserving a rail-to-rail output swing. The fabricated NCM Amplifier demonstrates 33x higher GBW and 47dB higher DC gain than those of a typical differential-pair (DP) Amplifier at equal power and area. By benchmarking with the recent three-Stage Amplifiers, this work improves FOM1 [=GBW.CL/(Power.Area)] by >6.6x, and upholds a comparable FOM2 [=SR.CL/(Power.Area)]. The CL drivability is >10x wider, while avoiding the stability limit at the heavy-CL side. These results justify advanced single-Stage Amplifiers as a potential replacement for multi-Stage designs in traditional (e.g. 100pF/m coaxial cable) and advanced (e.g. low temperature polysilicon LCD) buffer interfaces.
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ISCAS - Micropower two-Stage Amplifier employing recycling current-buffer Miller compensation
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Co-Authors: Wei Wang, Pui-in Mak, Man-kay Law, Zushu Yan, Rui P. MartinsAbstract:Proposed is a two-Stage Amplifier exploiting recycling current-buffer Miller compensation (CBMC). By reusing the most current-consuming devices in the 1 st Stage as current buffer, such an Amplifier not only can preserve the merits of typical CBMC implementation in creating the beneficial left-half-plane (LHP) zero, but also can avoid the drawbacks of typical CBMC scheme from degrading the power efficiency, DC gain, dc offset and noise performances. Optimized in 0.18μm CMOS via a low-power design procedure, the Amplifier achieves >90dB DC gain, 4.5MHz unity-gain frequency and 57.2° phase margin at a 100pF capacitive load. The average slew rate and 1% settling time are 2.68V/μs and 0.239μs, respectively. The Amplifier draws 22μA at a 1.2V supply.
