The Experts below are selected from a list of 66 Experts worldwide ranked by ideXlab platform
Tawfik Rahalarabi - One of the best experts on this subject based on the ideXlab platform.
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design and validation of the pentium sup spl reg iii and pentium sup spl reg 4 processors power delivery
Symposium on VLSI Circuits, 2002Co-Authors: Tawfik Rahalarabi, Gregory F Taylor, Clair WebbAbstract:In this paper, we present an empirical approach for the validation of the power Supply Impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.
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design validation of the pentium iii and pentium 4 processors power delivery
Symposium on VLSI Circuits, 2002Co-Authors: Tawfik RahalarabiAbstract:In this paper, we present an empirical approach for the validation of the power Supply Impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium ® III and Pentium ® 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.
Elad Alon - One of the best experts on this subject based on the ideXlab platform.
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a sub ns response fully integrated battery connected switched capacitor voltage regulator delivering 0 19w mm 2 at 73 efficiency
International Solid-State Circuits Conference, 2013Co-Authors: John Crossley, Seth R Sanders, Elad AlonAbstract:Lithium-ion batteries are the dominant power source in mobile devices. However, while the Supply voltage required for processors and SoCs has scaled down to ~1V, the voltage range of this popular battery remains ~2.9V-4.2V (nominally ~3.6V). To bridge this voltage difference, off-chip power management ICs are typically required. Despite their high efficiency, supporting many independent, high-current supplies to e.g. a multi-core SoC is extremely challenging due to cost, area, and Supply Impedance concerns associated with board and package level parasitics. There is hence strong motivation for efficient, fully integrated voltage regulators (IVRs) that interface directly with the battery while supporting multiple separate on-chip Supply.
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a 32nm fully integrated reconfigurable switched capacitor dc dc converter delivering 0 55w mm 2 at 81 efficiency
International Solid-State Circuits Conference, 2010Co-Authors: M Seeman, Seth R Sanders, Visvesh S Sathe, Samuel D Naffziger, Elad AlonAbstract:With the rising integration levels used to increase digital processing performance, there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. Simply adding multiple off-chip DCDC converters is not only difficult due to Supply Impedance concerns, but also adds cost to the platform by increasing motherboard size and package complexity. There is therefore a strong motivation to integrate voltage conversion blocks on the silicon chip.
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integrated regulation for energy efficient digital circuits
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Elad Alon, Mark HorowitzAbstract:Despite their use in analog or mixed-signal applications, the high power overheads of traditional linear regulators (both series and shunt) have precluded their successful adoption in regulating the Supply of energy-efficient digital circuits. In this paper, we show that linear regulation can in fact reduce the effective Supply Impedance of digital circuits without increasing their total power dissipation. Achieving this goal requires minimizing the static power dissipation of the regulator, leading to a push-pull topology (similar to the regulators demonstrated by Wu and Sanders, 2001, Poon et al, 1999, and Intersil, 1998) with comparator-based feedback and a switched source-follower output stage. Measured results from a regulator implemented in a 65 nm SOI test-chip verify that by using these techniques, regulation reduces the effective Supply noise by ~30% while also enabling a slight decrease (1.4%) in total power dissipation.
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integrated regulation for energy efficient digital circuits
Custom Integrated Circuits Conference, 2007Co-Authors: Elad Alon, Mark HorowitzAbstract:Linear regulation can reduce the effective Supply Impedance of digital circuits without increasing their total power dissipation. This can be achieved with a push-pull regulator topology that uses a second, higher-than-nominal Supply, comparator-based feedback, and a switched-source follower output stage. Measured results from a 65 nm SOI test-chip verify that by using these techniques, regulation reduces Supply noise by ~30% while also enabling a slight decrease (~1.4%) in total power.
Clair Webb - One of the best experts on this subject based on the ideXlab platform.
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design and validation of the pentium sup spl reg iii and pentium sup spl reg 4 processors power delivery
Symposium on VLSI Circuits, 2002Co-Authors: Tawfik Rahalarabi, Gregory F Taylor, Clair WebbAbstract:In this paper, we present an empirical approach for the validation of the power Supply Impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.
Mark Horowitz - One of the best experts on this subject based on the ideXlab platform.
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integrated regulation for energy efficient digital circuits
IEEE Journal of Solid-state Circuits, 2008Co-Authors: Elad Alon, Mark HorowitzAbstract:Despite their use in analog or mixed-signal applications, the high power overheads of traditional linear regulators (both series and shunt) have precluded their successful adoption in regulating the Supply of energy-efficient digital circuits. In this paper, we show that linear regulation can in fact reduce the effective Supply Impedance of digital circuits without increasing their total power dissipation. Achieving this goal requires minimizing the static power dissipation of the regulator, leading to a push-pull topology (similar to the regulators demonstrated by Wu and Sanders, 2001, Poon et al, 1999, and Intersil, 1998) with comparator-based feedback and a switched source-follower output stage. Measured results from a regulator implemented in a 65 nm SOI test-chip verify that by using these techniques, regulation reduces the effective Supply noise by ~30% while also enabling a slight decrease (1.4%) in total power dissipation.
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integrated regulation for energy efficient digital circuits
Custom Integrated Circuits Conference, 2007Co-Authors: Elad Alon, Mark HorowitzAbstract:Linear regulation can reduce the effective Supply Impedance of digital circuits without increasing their total power dissipation. This can be achieved with a push-pull regulator topology that uses a second, higher-than-nominal Supply, comparator-based feedback, and a switched-source follower output stage. Measured results from a 65 nm SOI test-chip verify that by using these techniques, regulation reduces Supply noise by ~30% while also enabling a slight decrease (~1.4%) in total power.
Gregory F Taylor - One of the best experts on this subject based on the ideXlab platform.
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design and validation of the pentium sup spl reg iii and pentium sup spl reg 4 processors power delivery
Symposium on VLSI Circuits, 2002Co-Authors: Tawfik Rahalarabi, Gregory F Taylor, Clair WebbAbstract:In this paper, we present an empirical approach for the validation of the power Supply Impedance model. The model is widely used to design the power delivery for high performance systems. For this purpose, several silicon wafers of the Pentium/sup /spl reg// III and Pentium/sup /spl reg// 4 processors were built with various amount of decoupling. The measured data showed significant discrepancies with the model predictions and provided useful insights in investigating the model regions of validity.
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an approach to measuring power Supply Impedance of microprocessors
Electrical Performance of Electronic Packaging, 2001Co-Authors: Gregory F Taylor, C Deutschle, Tawfik Arabi, B OwensAbstract:A technique to calculate the relative on die power Supply Impedance of high power CMOS integrated circuits as a function of frequency is described. This approach uses the power Supply current variation that is normally present in a microprocessor to stimulate the Supply network, varying the clock rate of the processor in order to obtain multiple measurements. Using this technique the power Supply Impedance vs. frequency of a 0.18 /spl mu/m microprocessor was measured and compared to a simple lumped circuit model.
