The Experts below are selected from a list of 14994 Experts worldwide ranked by ideXlab platform
E.g. Friedman - One of the best experts on this subject based on the ideXlab platform.
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Utilizing interdependent timing constraints to enhance robustness in Synchronous Circuits
Microelectronics Journal, 2012Co-Authors: Emre Salman, E.g. FriedmanAbstract:Interdependent setup-hold times are exploited during the design process to improve the robustness of a Circuit. Considering this interdependence only during static timing analysis (STA), as demonstrated in the previous work, is insufficient to fully exploit the capabilities offered by interdependence. This result is due to the strong dependence of STA results on the specific Circuit, cell library, and operating frequency. Interdependence is evaluated in this paper for several technologies to determine the overall reduction in delay uncertainty rather than improvements in STA. Reducing delay uncertainty produces a more robust Synchronous Circuit. The increasing efficacy of interdependence in deeply scaled technologies is also demonstrated by investigating the effect of technology scaling on interdependent timing constraints.
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retiming with non zero clock skew variable register and interconnect delay
International Conference on Computer Aided Design, 1994Co-Authors: Tolga Soyata, E.g. FriedmanAbstract:A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delay. These delay components are incorporated into retiming by assigning Register Electrical Characteristics (RECs) to each edge in the graph representation of the Synchronous Circuit. A matrix (called the Sequential Adjacency Matrix or SAM) is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in standard retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. The algorithm is demonstrated on modified MCNC benchmark Circuits and both increased clock frequencies and elimination of all race conditions are observed.
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ICCAD - Retiming with non-zero clock skew, variable register, and interconnect delay
IEEE ACM International Conference on Computer-Aided Design, 1994Co-Authors: Tolga Soyata, E.g. FriedmanAbstract:A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delay. These delay components are incorporated into retiming by assigning Register Electrical Characteristics (RECs) to each edge in the graph representation of the Synchronous Circuit. A matrix (called the Sequential Adjacency Matrix or SAM) is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in standard retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. The algorithm is demonstrated on modified MCNC benchmark Circuits and both increased clock frequencies and elimination of all race conditions are observed.
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ISCAS - Integration of clock skew and register delays into a retiming algorithm
1993 IEEE International Symposium on Circuits and Systems, 1993Co-Authors: Tolga Soyata, E.g. Friedman, J.h. MulliganAbstract:The clock frequency of a Synchronous Circuit can be increased by retiming, an operation of temporally and physically relocating the registers. A new approach to the retiming process is presented which enables one to consider the effects on optimal retiming of electrical issues such as variable clock distribution delays and different register delays due to variable loads and cell instances. The algorithm provides increased accuracy in determining the maximum clock frequency and also eliminates any race conditions. Depending on the nature of the Synchronous Circuit, retiming using this algorithms may also provide an increase in system operating clock frequency. >
Tolga Soyata - One of the best experts on this subject based on the ideXlab platform.
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retiming with non zero clock skew variable register and interconnect delay
International Conference on Computer Aided Design, 1994Co-Authors: Tolga Soyata, E.g. FriedmanAbstract:A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delay. These delay components are incorporated into retiming by assigning Register Electrical Characteristics (RECs) to each edge in the graph representation of the Synchronous Circuit. A matrix (called the Sequential Adjacency Matrix or SAM) is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in standard retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. The algorithm is demonstrated on modified MCNC benchmark Circuits and both increased clock frequencies and elimination of all race conditions are observed.
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ICCAD - Retiming with non-zero clock skew, variable register, and interconnect delay
IEEE ACM International Conference on Computer-Aided Design, 1994Co-Authors: Tolga Soyata, E.g. FriedmanAbstract:A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delay. These delay components are incorporated into retiming by assigning Register Electrical Characteristics (RECs) to each edge in the graph representation of the Synchronous Circuit. A matrix (called the Sequential Adjacency Matrix or SAM) is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in standard retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. The algorithm is demonstrated on modified MCNC benchmark Circuits and both increased clock frequencies and elimination of all race conditions are observed.
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ISCAS - Integration of clock skew and register delays into a retiming algorithm
1993 IEEE International Symposium on Circuits and Systems, 1993Co-Authors: Tolga Soyata, E.g. Friedman, J.h. MulliganAbstract:The clock frequency of a Synchronous Circuit can be increased by retiming, an operation of temporally and physically relocating the registers. A new approach to the retiming process is presented which enables one to consider the effects on optimal retiming of electrical issues such as variable clock distribution delays and different register delays due to variable loads and cell instances. The algorithm provides increased accuracy in determining the maximum clock frequency and also eliminates any race conditions. Depending on the nature of the Synchronous Circuit, retiming using this algorithms may also provide an increase in system operating clock frequency. >
Mehdi Sedighi - One of the best experts on this subject based on the ideXlab platform.
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FPGA - Prototyping globally aSynchronous locally Synchronous Circuits on commercial Synchronous FPGAs (abstract only)
Proceedings of the 2005 ACM SIGDA 13th international symposium on Field-programmable gate arrays - FPGA '05, 2005Co-Authors: Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi SedighiAbstract:This paper introduces a methodology for prototyping Globally ASynchronous Locally Synchronous (GALS) Circuits on Synchronous commercial FPGAs. A library of required elements for implementing GALS Circuits is proposed and general design considerations to successfully implement a GALS Circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these Circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the Circuit by 11% and reduces the power consumption by 18.7% to 19.6% considering different error rates. On the other hand, the area of the Circuit is increased by 51% which is acceptable considering that a pure Synchronous Circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.
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IEEE International Workshop on Rapid System Prototyping - Prototyping globally aSynchronous locally Synchronous Circuits on commercial Synchronous FPGAs
16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 1Co-Authors: Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi SedighiAbstract:This paper introduces a methodology for prototyping globally aSynchronous locally Synchronous (GALS) Circuits on Synchronous commercial FPGAs. A library of required elements for implementing GALS Circuits is proposed and general design considerations to successfully implement a GALS Circuit on FPGA are discussed. The library includes clock generators and arbiters, and different port controllers. Different implementations of these Circuits and their advantages and disadvantages are explored. At the end we present a GALS Reed-Solomon decoder as a practical example. The results show that the GALS approach improves the performance of the Circuit by 11% and reduces the power consumption by 18.7% to 19,6% considering different error rates. On the other hand, the area of the Circuit is increased by 51% which is acceptable considering that a pure Synchronous Circuit including a central controller is decomposed to generate GALS system and 29% of this overhead belongs to distributing controller in different modules. Deploying better decomposition methods can reduce this overhead substantially.
Zhan Yue - One of the best experts on this subject based on the ideXlab platform.
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Design of Phase-locked Synchronous Circuit in Single-phase UPS
IEEE Transactions on Power Electronics, 2001Co-Authors: Zhan YueAbstract:Based on the practice of designing single phase uninterruptable power supply(UPS), this paper introduces design of phase locked Synchronous Circuit for off line square wave UPS, on line USP equipped with and without output transformer.
Song Guo - One of the best experts on this subject based on the ideXlab platform.
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A Improvement of Thyristor Trigger Based on Synchronous Circuit of Phase Locked Loop
Journal of Xingjiang University, 2002Co-Authors: Song GuoAbstract:The paper is aimed at the ZX5 and ZL5 series thyistor welder with a Synchronous Circuit of phase locked loop and frequency multiplier. When connecting welder with the power system, correct phase order is needed, or else the device doesn't work right. In this paper, some reasons are analyzed, improvement proposal is presented and the validity of the proposal is verified by experiments.
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An improvement on thyristor trigger based on Synchronous Circuit of phase locked loop
Electric Welding Machine, 2001Co-Authors: Song GuoAbstract:The paper is aimed at the ZX5 and ZL5 Series thyristor welder with a Synchronous Circuit of phase locked loop and frequency multiplier.When the welder is connected with the power system,correct phase order is needed,or else the device doesn't work well.In this paper,some reasons are analyzed,improvement proposal is presented and the validity of the proposal was verified by experiments.
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The Improvement of Thyristor Power Supply Device Based on Synchronous Circuit of Phase Locked Loop and Frequency Multiplier
Journal of Henan Mechanic and Electric Engineering College, 2001Co-Authors: Song GuoAbstract:The paper aims at the thyristor power supply device witha Synchronous Circuit of phase locked loop and frequency multiplier .When the power supply device is connected with the power system ,correct phase order is needed;otherwise the device doesn't work right. In this paper,some reasons are analyzed , improvement proposal is resented and the validity of the proposal is verified by experiments.
