The Experts below are selected from a list of 4014 Experts worldwide ranked by ideXlab platform
Keivan Navi - One of the best experts on this subject based on the ideXlab platform.
-
design of two low power Full Adder cells using gdi structure and hybrid cmos logic style
Integration, 2014Co-Authors: Vahid Foroutan, Keivan Navi, Mohammadreza Taheri, Arash Azizi MazreahAbstract:Full Adder is one of the most important digital components for which many improvements have been made to improve its architecture. In this paper, we present two new symmetric designs for Low-Power Full Adder cells featuring GDI (Gate-Diffusion Input) structure and hybrid CMOS logic style. The main design objectives for these Adder modules are not only providing Low-Power dissipation and high speed but also Full-voltage swing. In the first design, hybrid logic style is employed. The hybrid logic style utilizes different logic styles in order to create new Full Adders with desired performance. This provides the designer with a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second design is based on a different new approach which eliminates the need of XOR/XNOR gates for designing Full Adder cell and also by utilizing GDI (Gate-Diffusion-Input) technique in its structure, it provides Ultra Low-Power and high speed digital component as well as a Full voltage swing circuit. Many of the previously reported Adders in literature suffered from the problems of low-swing and high noise when operated at low supply voltages. These two new designs successFully operate at low voltages with tremendous signal integrity and driving capability. In order to evaluate the performance of the two new Full Adders in a real environment, we incorporated two 16-bit ripple carry Adders (RCA). The studied circuits are optimized for energy efficiency at 0.13@?m and 90nm PD SOI CMOS process technology. The comparison between these two novel circuits with standard Full Adder cells shows excessive improvement in terms of Power, Area, Delay and Power-Delay-Product (PDP).
-
an efficient quantum dot cellular automata Full Adder
2012Co-Authors: Sara Hashemi, Mohammad A Tehrani, Keivan NaviAbstract:The most important mathematical operation is addition. Other operations such as subtraction, multiplication and division are usually implemented by Adders. An efficient Adder can be of great assistance in designing arithmetic circuits. QCA is a promising technology which seems to be a good candidate for the next generation of digital systems. So, an efficient QCA Full-Adder will facilitate creating QCA computational and arithmetic systems. In this paper, two high performances QCA FullAdders are presented. They have a very dense structure and constructed using new kinds of five-input majority gates. One of the proposed designs has a robust structure. In this design the presented design rules for constructing a robust QCA circuit have been considered. In contrast to the previous designs constructed using a five-input majority gate, in the proposed QCA Full-Adders the outputs come out from the same side of the circuit. Also, the input and output signals are not surrounded by the other cells and can easily be accessed. The proposed robust QCA Full-Adder dominates all the previous robust designs in terms of area, delay and complexity. Using this design, ripple carry Adders with different word sizes (that is, 4, 8 and 16) are constructed. In this paper, QCA designer, a common QCA layout design and verification tool is employed to verify and simulate the proposed five-input majority gates and QCA Full-Adders.
-
efficient cntfet based ternary Full Adder cells for nanoelectronics
Nano-micro Letters, 2011Co-Authors: Mohammad Hossein Moaiyeri, Keivan Navi, Reza Faghih Mirzaee, Omid HashemipourAbstract:This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFET-based ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
-
a novel low power Full Adder cell with new technique in designing logical gates based on static cmos inverter
Microelectronics Journal, 2009Co-Authors: Keivan Navi, Vahid Foroutan, Rahimi M Azghadi, Mehrdad Maeen, M Ebrahimpour, M Kaveh, Omid KaveheiAbstract:A new low-power Full-Adder based on CMOS inverter is presented. This Full-Adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As Full-Adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the Full-Adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using [email protected] and 90nm CMOS process technologies. The proposed Full-Adder shows Full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively.
-
a novel low power Full Adder cell for low voltage
Integration, 2009Co-Authors: Keivan Navi, Somayeh Timarchi, Vahid Foroutan, Mehrdad Maeen, Omid KaveheiAbstract:This paper presents a novel low-power majority function-based 1-bit Full Adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-@mm CMOS process technology. The Adder cell is compared with seven widely used Adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new Adder has more than 11% in power savings over a conventional 28-transistor CMOS Adder. In addition, it consumes 30% less power than transmission function Adder (TFA) and is 1.11 times faster.
Majid Haghparast - One of the best experts on this subject based on the ideXlab platform.
-
an efficient design of reversible ternary Full Adder Full subtractor with low quantum cost
Quantum Information Processing, 2020Co-Authors: Mohammadali Asadi, Mohammad Mosleh, Majid HaghparastAbstract:One of the major challenges of VLSI circuits is heat caused by energy loss. One of the successful solutions to this challenge is to design circuits in a reversible manner. Hence, the design of reversible circuits has attracted the attention of many researchers in the fields of low-power circuits design, DNA computing and quantum computing. Due to the benefits of ternary logic over binary logic such as reducing the complexity of interconnecting circuits, decreasing the occupied surface and reducing the number of quantum cells in quantum circuits, the ternary logic has been proposed for the design of VLSI circuits. In this paper, we first propose a new reversible ternary Full-Adder, called comprehensive reversible ternary Full-Adder, using the ternary logic capabilities. In the following, an efficient reversible ternary Full-subtractor is provided. Finally, using the two proposed circuits, a new reversible ternary Full-Adder/Full-subtractor is introduced. The results of the comparisons show that the proposed circuits have lower quantum cost and are more efficient than the other previous circuits.
-
quaternary quantum reversible half Adder Full Adder parallel Adder and parallel Adder subtractor circuits
International Journal of Theoretical Physics, 2019Co-Authors: Asma Taheri Monfared, Majid Haghparast, Kamalika DattaAbstract:Multiple valued quantum logic is a promising research area in quantum computing technology having several advantages over binary quantum logic. Adder circuits as well as subtractor circuits are the major components of various computational units in computers and other complex computational systems. In this paper, we propose a quaternary quantum reversible half-Adder circuit using quaternary 1-qudit gates, 2-qudit Feynman and Muthukrishnan-Stroud gates. Then we propose a quaternary quantum reversible Full Adder and a quaternary quantum parallel Adder circuit. In addition, we propose a quaternary quantum reversible parallel Adder/subtractor circuit. The proposed designs are compared with existing designs and improvements in terms of hardware complexity, quantum cost, number of constant inputs and garbage outputs are reported.
-
optimized parity preserving quantum reversible Full Adder subtractor
International Journal of Quantum Information, 2016Co-Authors: Majid Haghparast, Ali BolhassaniAbstract:Reversible logic is one of the indispensable aspects of emerging technologies for reducing physical entropy gain, since reversible circuits do not lose information in the form of internal heat during computation. This paper aimed to initiate constructing parity preserving reversible circuits. A novel parity preserving reversible block, HB is presented. Then a new design of a cost-effective parity preserving reversible Full Adder/subtractor (PPFA/S) is proposed. Next, we suggested a new parity preserving binary to BCD converter. Finally, we proposed new realization of parity preserving reversible BCD Adder. The proposed designs are cost-effective in terms of quantum cost and delay. All the scales are in the NANO-metric area.
Hosseinzadeh M. - One of the best experts on this subject based on the ideXlab platform.
-
Two novel inverter-based ternary Full Adder cells using CNFETs for energy-efficient applications
Taylor and Francis Ltd., 2020Co-Authors: Mahmoudi Salehabad, Navi K., Hosseinzadeh M.Abstract:Carbon nanotube field effect transistors (CNFETs) exhibit great promise and extensions to silicon MOSFET due to their excellent electronic properties and extremely small size. Implementable CNFET circuits have operational characteristics to approach the advantage of using multiple-valued logic (MVL) in voltage mode. In MVL implementation computation for the system will be faster than the binary system with improved density of digital circuits. This paper presents two novel 1-bit inverter-based ternary Full Adder cells which second design cell uses only 37 CNFET transistors in its structure. These designs have been proposed using a new definition of Majority-not based Full Adder, and are compared to the other Adders based on power consumption, speed and power-delay product (PDP). Proposed designs are evaluated using simulation run on HSPICE with 32 nm CNFET standard technology under various operational conditions, including different supply voltages, output load variation and different operating temperatures. According to simulation results, all proposed ternary Full Adder designs in compare to the state of the art circuits in literature have been demonstrated up to 81 and 80, respectively, improvement in power consumption and PDP. © 2019, © 2019 Informa UK Limited, trading as Taylor & Francis Group
-
A low-power high-speed hybrid multi-threshold Full Adder design in CNFET technology
2018Co-Authors: Maleknejad M., Navi K., Mohammadi S., Mirhosseini S.m., Naji H.r., Hosseinzadeh M.Abstract:In this paper, a low-power high-speed hybrid Full Adder cell is proposed, which is implemented based on two-input multi-threshold (Formula presented.) XNOR circuit and transmission gate multiplexers. In order to implement this circuit, carbon nanotube field-effect transistors are utilized. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects of digital circuits: power, delay and power�delay product. The results are presented and confirm the superiority of the proposed cell with the previously reported one in different voltage levels, load conditions, temperatures and robustness in large structures and against process variations. © 2018 Springer Science+Business Media, LLC, part of Springer Natur
-
A low-power high-speed hybrid multi-threshold Full Adder design in CNFET technology
2018Co-Authors: Maleknejad M., Navi K., Mohammadi S., Mirhosseini S.m., Naji H.r., Hosseinzadeh M.Abstract:In this paper, a low-power high-speed hybrid Full Adder cell is proposed, which is implemented based on two-input multi-threshold (Vt) XNOR circuit and transmission gate multiplexers. In order to implement this circuit, carbon nanotube field-effect transistors are utilized. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects of digital circuits: power, delay and power�delay product. The results are presented and confirm the superiority of the proposed cell with the previously reported one in different voltage levels, load conditions, temperatures and robustness in large structures and against process variations. © 2018, Springer Science+Business Media, LLC, part of Springer Nature
-
A CNFET-based hybrid multi-threshold 1-bit Full Adder design for energy efficient low power applications
2018Co-Authors: Maleknejad M., Navi K., Mohammadi S., Naji H.r., Hosseinzadeh M.Abstract:In this article, a low-power and energy-efficient hybrid Full Adder circuit is proposed, which is implemented based on multi-threshold NAND and NOR gates and transmission gate multiplexers. In order to implement this circuit, carbon nano tube field effect transistors are utilised. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects power, delay and power-delay product. The results are presented and displayed the superiority of the proposed cell in different voltage levels, load conditions, temperatures and robustness against process variations. © 2018, © 2018 Informa UK Limited, trading as Taylor & Francis Group
-
A Full Adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis
2018Co-Authors: Asfestani M.n., Hosseinzadeh M.Abstract:Quantum-dot cellular automata (QCA) is the appearance of new technology and can be a suitable alternative to semiconductor transistor technology. In this paper, the new structure of the two-input XOR gate is presented, which is the modified version of the three-input XOR gate. This structure can be used to design various useful QCA circuits. By utilizing this gate, we design and implement a new Full Adder structure with 90-degree cells. This structure is designed in a single layer without cross-wiring. The operation of the proposed structure has been verified by QCADesigner version 2.0.3 and energy dissipation investigated by QCAPro tool. We also compared the effectiveness of our structure with the two previous structures. © 2017, Springer Science+Business Media, LLC, part of Springer Nature
Mohammad Hossein Moaiyeri - One of the best experts on this subject based on the ideXlab platform.
-
design of an ultra efficient reversible Full Adder subtractor in quantum dot cellular automata
Optik, 2017Co-Authors: Elham Taherkhani, Mohammad Hossein Moaiyeri, Shaahin AngiziAbstract:Abstract By the progressive scaling of the feature size and power consumption in VLSI chips the part of energy dissipated due to information loss in irreversible computations will become a serious limitation in the near future. Quantum-dot cellular automata (QCA) is an emerging nanotechnology with extremely low energy dissipation which facilitates new computation paradigms such as reversible computing. In this paper a novel reversible Full Adder-subtractor circuit based on QCA is proposed. Our proposed design is implemented using only one layer and does not require any rotated cells which significantly improves the manufacturability of the design. In addition, it improves the cell count, area and total energy dissipation by almost 45% and 50% and 48%, respectively, as compared to the existing QCA-based single-layer and multilayer reversible Full Adders.
-
a novel efficient reversible Full Adder subtractor in qca nanotechnology
arXiv: Emerging Technologies, 2016Co-Authors: Mohammad Hossein Moaiyeri, Elham Taherkhani, Shaahin AngiziAbstract:By the progressive scaling of the feature size and power consumption in VLSI chips the part of energy dissipated due to information loss in irreversible computations will become a serious limitation in the near future. Quantum-dot cellular automata (QCA) is an emerging nanotechnology with extremely low energy dissipation which facilitates new computation paradigms such as reversible computing. In this letter a novel reversible Full Adder-subtractor circuit based on QCA is proposed. Our proposed design is implemented using only one layer and does not require any rotated cells which significantly improves the manufacturability of the design. In addition, it improves the cell count and area by almost 45% and 50%, respectively, as compared to the existing QCA-based single-layer and multilayer reversible Full Adders.
-
efficient cntfet based ternary Full Adder cells for nanoelectronics
Nano-micro Letters, 2011Co-Authors: Mohammad Hossein Moaiyeri, Keivan Navi, Reza Faghih Mirzaee, Omid HashemipourAbstract:This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFET-based ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
Omid Hashemipour - One of the best experts on this subject based on the ideXlab platform.
-
efficient cntfet based ternary Full Adder cells for nanoelectronics
Nano-micro Letters, 2011Co-Authors: Mohammad Hossein Moaiyeri, Keivan Navi, Reza Faghih Mirzaee, Omid HashemipourAbstract:This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFET-based ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
