The Experts below are selected from a list of 51 Experts worldwide ranked by ideXlab platform
H.j. Liao - One of the best experts on this subject based on the ideXlab platform.
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A high-speed BiCMOS Tristate Buffer
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1993Co-Authors: H.j. LiaoAbstract:A high-speed BiCMOS Tristate Buffer with a single bipolar device pull-up structure for driving a large capacitive load is presented. According to SPICE simulation results, the Buffer, which occupies about an identical area, has a 2*improvement in delay time as compared to the CMOS Tristate Buffer.
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A BiCMOS Tristate Buffer for high-speed microprocessor VLSI
[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit, 1991Co-Authors: H.j. LiaoAbstract:This paper presents a high speed BiCMOS Tristate Buffer with a single bipolar device pull-up structure for driving a bus with a large capacitive load. With the new pull-structure, the BiCMOS Tristate Buffer, which is suitable for microprocessor VLSI, has an improvement in delay time of 30% compared with the standard BiCMOS Tristate Buffer.
Kobchai Dejhan - One of the best experts on this subject based on the ideXlab platform.
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a high speed bootstrapped bicmos Tristate Buffer circuit
ITC-CSCC :International Technical Conference on Circuits Systems Computers and Communications, 2007Co-Authors: Jetsarawoot Kreuakun, Siraphop Tooprakai, Sorawat Chivapreecha, Somyot Junnapiya, Kobchai DejhanAbstract:This paper proposes a high-speed bootstrapped BiCMOS Tristate Buffer circuit for driving a large capacitive load. The driving sections are designed by using the noncomplementary BiCMOS technology. In enable and disable sections are using CMOS NAND with CMOS NOR circuit. The bipolar pull up driving section are driven by bootstrapped CMOS circuit. Therefore, the proposed circuit can be feblicated on standard BiCMOS technology and this circuit has high speed operation and operates on 1.5 volt, the circuit time delay performances are investigated by using PSpice program.
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A high speed and low voltage BiCMOS Tristate Buffer with positive and negative charge pump
ICECS 2000. 7th IEEE International Conference on Electronics Circuits and Systems (Cat. No.00EX445), 2000Co-Authors: C. Suriyaammaranon, Kobchai Dejhan, F. Cheevasuvit, C. SoonyeekanAbstract:A novel high speed, low voltage BiCMOS Tristate Buffer is presented. The single MOS driving with pass transistor technique is used to improve the driving capability. Furthermore, the positive and negative charge pump with complementary BiCMOS technique to eliminate the voltage loss due to base-emitter turn on voltage is used to enhance the driving capability and realize high speed, low voltage with full swing operation. The simulation results have shown that it outperforms other previous Tristate circuits.
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A high speed BiCMOS Tristate Buffer circuit
ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics Circuits and Systems (Cat. No.99EX357), 1999Co-Authors: C. Suriyaammaranon, Kobchai Dejhan, F. Cheevasuvit, C. SoonyeekanAbstract:This paper presents a novel high speed BiCMOS Tristate Buffer for driving a large capacitive load by using the pass transistor technique to achieve a single MOS driving bipolar transistor. With a single MOS driving, it can increase the driving capability as well as reduce the number of large MOS transistors that are required to drive a bipolar compared with previous designs. In addition, the feedback circuit to achieve a full-swing operation from supply voltage to ground is added. The simulation results for the switching characteristics, rise time, fall time and base current during enable as well as the voltage waveform during disable have been presented.
C. Soonyeekan - One of the best experts on this subject based on the ideXlab platform.
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A high speed and low voltage BiCMOS Tristate Buffer with positive and negative charge pump
ICECS 2000. 7th IEEE International Conference on Electronics Circuits and Systems (Cat. No.00EX445), 2000Co-Authors: C. Suriyaammaranon, Kobchai Dejhan, F. Cheevasuvit, C. SoonyeekanAbstract:A novel high speed, low voltage BiCMOS Tristate Buffer is presented. The single MOS driving with pass transistor technique is used to improve the driving capability. Furthermore, the positive and negative charge pump with complementary BiCMOS technique to eliminate the voltage loss due to base-emitter turn on voltage is used to enhance the driving capability and realize high speed, low voltage with full swing operation. The simulation results have shown that it outperforms other previous Tristate circuits.
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A high speed BiCMOS Tristate Buffer circuit
ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics Circuits and Systems (Cat. No.99EX357), 1999Co-Authors: C. Suriyaammaranon, Kobchai Dejhan, F. Cheevasuvit, C. SoonyeekanAbstract:This paper presents a novel high speed BiCMOS Tristate Buffer for driving a large capacitive load by using the pass transistor technique to achieve a single MOS driving bipolar transistor. With a single MOS driving, it can increase the driving capability as well as reduce the number of large MOS transistors that are required to drive a bipolar compared with previous designs. In addition, the feedback circuit to achieve a full-swing operation from supply voltage to ground is added. The simulation results for the switching characteristics, rise time, fall time and base current during enable as well as the voltage waveform during disable have been presented.
T.j. Powell - One of the best experts on this subject based on the ideXlab platform.
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VTS - Consistently dominant fault model for Tristate Buffer nets
Proceedings of 14th VLSI Test Symposium, 1996Co-Authors: T.j. PowellAbstract:Unknown values result from floating and contention type faults on Tristate Buffer nets thereby causing MISR signature loss during test pattern compression. A Consistently Dominant Fault model is presented that removes the problem and permits fault detection of several problem Tristate Buffer stuck faults.
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Consistently dominant fault model for Tristate Buffer nets
Proceedings of 14th VLSI Test Symposium, 1996Co-Authors: T.j. PowellAbstract:Unknown values result from floating and contention type faults on Tristate Buffer nets thereby causing MISR signature loss during test pattern compression. A Consistently Dominant Fault model is presented that removes the problem and permits fault detection of several problem Tristate Buffer stuck faults.
C. Suriyaammaranon - One of the best experts on this subject based on the ideXlab platform.
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A high speed and low voltage BiCMOS Tristate Buffer with positive and negative charge pump
ICECS 2000. 7th IEEE International Conference on Electronics Circuits and Systems (Cat. No.00EX445), 2000Co-Authors: C. Suriyaammaranon, Kobchai Dejhan, F. Cheevasuvit, C. SoonyeekanAbstract:A novel high speed, low voltage BiCMOS Tristate Buffer is presented. The single MOS driving with pass transistor technique is used to improve the driving capability. Furthermore, the positive and negative charge pump with complementary BiCMOS technique to eliminate the voltage loss due to base-emitter turn on voltage is used to enhance the driving capability and realize high speed, low voltage with full swing operation. The simulation results have shown that it outperforms other previous Tristate circuits.
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A high speed BiCMOS Tristate Buffer circuit
ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics Circuits and Systems (Cat. No.99EX357), 1999Co-Authors: C. Suriyaammaranon, Kobchai Dejhan, F. Cheevasuvit, C. SoonyeekanAbstract:This paper presents a novel high speed BiCMOS Tristate Buffer for driving a large capacitive load by using the pass transistor technique to achieve a single MOS driving bipolar transistor. With a single MOS driving, it can increase the driving capability as well as reduce the number of large MOS transistors that are required to drive a bipolar compared with previous designs. In addition, the feedback circuit to achieve a full-swing operation from supply voltage to ground is added. The simulation results for the switching characteristics, rise time, fall time and base current during enable as well as the voltage waveform during disable have been presented.
