The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform
Y. Harada - One of the best experts on this subject based on the ideXlab platform.
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a 0 8 w hdtv Video Processor with simultaneous decoding of two mpeg2 mp hl streams and capable of 30 frames s reverse playback
International Solid-State Circuits Conference, 2002Co-Authors: Hideki Yamauchi, K. Taketa, Y. Harada, Shigeyuki Okada, Y. Matsuda, T. Mori, T. Watanabe, M. Matsudaira, Y. MatsushitaAbstract:A HDTV Video Processor with decoding/display of two MPEG MP@HL streams and reverse playback with smooth 30 frames/s without frame skip uses a 0.18 /spl mu/m 5-layer process in 6.86/spl times/6.86 mm/sup 2/ and 5.7M transistors. It is for home multimedia and mobile TV applications. It operates at 135 MHz and 0.8 W at 1.8 V.
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A 0.8 W HDTV Video Processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30 frames/s reverse playback
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002Co-Authors: H. Yamauchi, K. Taketa, Y. Harada, Shigeyuki Okada, Y. Matsuda, T. Mori, Shin'ichiro Okada, T. Watanabe, M. Matsudaira, Y. MatsushitaAbstract:A HDTV Video Processor with decoding/display of two MPEG MP@HL streams and reverse playback with smooth 30 frames/s without frame skip uses a 0.18 /spl mu/m 5-layer process in 6.86/spl times/6.86 mm/sup 2/ and 5.7M transistors. It is for home multimedia and mobile TV applications. It operates at 135 MHz and 0.8 W at 1.8 V.
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Single chip Video Processor for digital HDTV
ICCE. International Conference on Consumer Electronics (IEEE Cat. No.01CH37182), 2001Co-Authors: H. Yamauchi, S. Okada, K. Taketa, Y. Mihara, Y. HaradaAbstract:We have developed a new high-performance Video system LSI using a 0.25 /spl mu/m CMOS technology for Japan BS digital broadcasting launched in December 2000. The LSI integrates all the necessary functions for Video decoding into a single chip and employs efficient architectures which are parallel processing and have parallel data bus architecture for decoding transport streams efficiently.
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Single chip Video Processor for digital HDTV
IEEE Transactions on Consumer Electronics, 2001Co-Authors: H. Yamauchi, S. Okada, K. Taketa, Y. Mihara, Y. HaradaAbstract:We have developed a single chip Video Processor integrated TS decoder, MPEG-2 MP@HL decoder and OSD controller for BS digital broadcasting. The Video Processor is available for all the formats of digital broadcasting and displays output on the "Hi-Vision" (high-definition) CRT in SDTV as well as HDTV. Also, 4-channel decoding/display and multi-angle broadcasting of digital TV is obtained. It has excellent functions such as seamless display, audio/Video (AV) synchronization, error concealment, etc. Adoption of a cooperative processing architecture with hardware and software, pipeline architecture and parallel bus architecture allows flexible support of operating frequency reduction, circuit miniaturization, design simplification, high-performance service of BS digital TV, digital TV broadcasting regulation change and equipment specification change. This single chip Video Processor is manufactured of 0.25-/spl mu/m four-layer metal CMOS process and the chip size is 10.2 mm/spl times/10.2 mm. The power consumption is 4.5 W when the supply voltage is 2.5 V and operating frequency is 121.5 MHz.
H. Miyaguchi - One of the best experts on this subject based on the ideXlab platform.
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EDTV-II decoder by SVP2 (the 2nd generation of scan-line Video Processor)
IEEE Transactions on Consumer Electronics, 1995Co-Authors: K. Nakayama, H. Miyaguchi, T. Kojima, T. Sawaragi, Y. YaguchiAbstract:SVP2 (the second generation scan-line Video Processor) is a general purpose programmable real-time Video Processor having 1024 processing elements on a single chip. It can perform 5.7-billion 8-bit addition in a second, and a full spec EDTV-II (the second generation enhanced definition TV in Japan) decoder was implemented by two SVP2.
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SVP: scan-line Video Processor-general purpose Video Processor
1995 International Symposium on VLSI Technology Systems and Applications. Proceedings of Technical Papers, 1995Co-Authors: H. Onuma, H. Miyaguchi, Y. Yaguchi, T. Kojima, T. Akiyama, K. Kajiyama, K. Adachi, A. Kikuchi, T. NarumiAbstract:The SVP achieved a fast processing rate exceeding standard DSPs by integrating 1024 PEs (Processing Elements). 50 MHz operation in each PE in the SIMD (Single Instruction Multiple Data) scheme is realized on two stage pipelines in the IG (Instruction Generator) and five stage pipelines in the PE CORE. With the realization of a 20 ns DRAM cycle in each PE and the system clock generated through a PLL, SVP enables full-spec-EDTV2 (the second generation Enhanced Definition Television in Japan).
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SVP: serial Video Processor
IEEE Proceedings of the Custom Integrated Circuits Conference, 1990Co-Authors: J. Childers, H. Miyaguchi, P. Reinecke, S. Yamamoto, Y. Takahashi, Y. Yaguchi, M. TakeyasuAbstract:Real-time Video signal processing is achieved by a serial Video Processor (SVP) which inputs/outputs Video signals serially and processes the data in parallel during each horizontal line period. This work describes the architecture of the SVP. An overview of the device, unique design techniques, and test methodology are given. Two SVPs applied to digital color TV image processing are discussed. Specifically, this is an Improved Definition TV application providing motion-adaptive digital Y/C separation, noise reduction, and progressive scanning. The addition of multiplexers in the appropriate data paths allows this same basic circuit to perform special features (still, strobe, zoom, picture-in-picture, multiscreen, etc.).
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Digital TV with serial Video Processor
IEEE Transactions on Consumer Electronics, 1990Co-Authors: H. Miyaguchi, H. Krasawa, S. Watanabe, J. Childers, P. Reinecke, M. BeckerAbstract:The serial Video Processor (SVP) is a general-purpose mask-programmable SIMD RISC (single instruction multiple-data, reduced instruction set computer) device capable of executing, in real time, the three-dimensional algorithms required for image processing and digital television. Its architecture, application, and development environment are described. Using this approach, the turn-around time to develop, evaluate, and produce a digital-based Video application is significantly reduced.
R.j. Gove - One of the best experts on this subject based on the ideXlab platform.
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The MVP: a highly-integrated Video compression chip
Proceedings of IEEE Data Compression Conference (DCC'94), 1994Co-Authors: R.j. GoveAbstract:The author introduces a new highly-integrated processing chip for performing a variety of functions, however this chip is particularly well suited for Video compression algorithms. Applications include multimedia PCs, virtual reality 3D graphics, full-duplex Videoconferencing, HDTV, and color hardcopy. He has architected the multimedia Video Processor, or MVP, to provide a yet unattainable level of performance from a single chip, although with the programmability typically found in today's general-purpose computers. While advanced semiconductor design and process techniques have been used for its design, the key to the advantage of this component lies in optimization of the architecture for real-time Video and graphics processing. He analyses Video compression application requirements, describe the MVP architecture, and poses its potential as a very capable solution for a wide range of markets.
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The Multimedia Video Processor (MVP): a chip architecture for advanced DSP applications
Proceedings of IEEE 6th Digital Signal Processing Workshop, 1994Co-Authors: R.j. GoveAbstract:The Texas Instruments Multimedia Video Processor (MVP), a single-chip multi-processing DSP for performing a variety of functions, provides unprecedented computing power and programmability. The MVP is particularly well suited for image and Video applications. Utilizing a flexible parallel architecture, the chip can satisfy many Video, audio, imaging and graphics functions, such as those required for desktop multimedia.
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MediaStation 5000: integrating Video and audio
IEEE MultiMedia, 1994Co-Authors: R.j. Gove, C.j. ReadAbstract:MediaStation 5000 is a highly integrated desktop multimedia system implemented on a single PC plug-in board. It performs multistandard compression, high-speed image processing, and fast 2D and 3D graphics functions. The Texas instruments Multimedia Video Processor (MVP), a single-chip multiprocessing device with a highly parallel internal architecture, provides the system's processing power and programmability.
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A single-chip multiProcessor for multimedia : the MVP : Semiconductor technology for graphics and imaging
IEEE Computer Graphics and Applications, 1992Co-Authors: Karl M. Guttag, R.j. Gove, J. R. Van AkenAbstract:We defined the multimedia Video Processor (MVP) to accelerate applications with heavy image and graphics processing requirements. Here we give an overview of the architecture
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A single-chip multiProcessor for multimedia: the MVP
IEEE Computer Graphics and Applications, 1992Co-Authors: Karl M. Guttag, R.j. Gove, J. R. Van AkenAbstract:The multimedia Video Processor (MVP) architecture, which incorporates a variety of parallel processing techniques to deliver very high performance to a wide range of imaging and graphics applications, is described. The MVP combines, on a single semiconductor chip, multiple fully programmable Processors with multiple data streams connected to shared RAMs through a crossbar network. Each of the independent Processors can execute many operations in parallel every cycle. The architecture is scalable and supports different numbers of Processors to meet the cost and performance requirements of different markets. MVP's target environment and the development of MVP are outlined.
Y. Yaguchi - One of the best experts on this subject based on the ideXlab platform.
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SVP: scan-line Video Processor-general purpose Video Processor
1995 International Symposium on VLSI Technology Systems and Applications. Proceedings of Technical Papers, 1995Co-Authors: H. Onuma, H. Miyaguchi, Y. Yaguchi, T. Kojima, T. Akiyama, K. Kajiyama, K. Adachi, A. Kikuchi, T. NarumiAbstract:The SVP achieved a fast processing rate exceeding standard DSPs by integrating 1024 PEs (Processing Elements). 50 MHz operation in each PE in the SIMD (Single Instruction Multiple Data) scheme is realized on two stage pipelines in the IG (Instruction Generator) and five stage pipelines in the PE CORE. With the realization of a 20 ns DRAM cycle in each PE and the system clock generated through a PLL, SVP enables full-spec-EDTV2 (the second generation Enhanced Definition Television in Japan).
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EDTV-II decoder by SVP2 (the 2nd generation of scan-line Video Processor)
IEEE Transactions on Consumer Electronics, 1995Co-Authors: K. Nakayama, H. Miyaguchi, T. Kojima, T. Sawaragi, Y. YaguchiAbstract:SVP2 (the second generation scan-line Video Processor) is a general purpose programmable real-time Video Processor having 1024 processing elements on a single chip. It can perform 5.7-billion 8-bit addition in a second, and a full spec EDTV-II (the second generation enhanced definition TV in Japan) decoder was implemented by two SVP2.
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SVP: serial Video Processor
IEEE Proceedings of the Custom Integrated Circuits Conference, 1990Co-Authors: J. Childers, H. Miyaguchi, P. Reinecke, S. Yamamoto, Y. Takahashi, Y. Yaguchi, M. TakeyasuAbstract:Real-time Video signal processing is achieved by a serial Video Processor (SVP) which inputs/outputs Video signals serially and processes the data in parallel during each horizontal line period. This work describes the architecture of the SVP. An overview of the device, unique design techniques, and test methodology are given. Two SVPs applied to digital color TV image processing are discussed. Specifically, this is an Improved Definition TV application providing motion-adaptive digital Y/C separation, noise reduction, and progressive scanning. The addition of multiplexers in the appropriate data paths allows this same basic circuit to perform special features (still, strobe, zoom, picture-in-picture, multiscreen, etc.).
H. Yamauchi - One of the best experts on this subject based on the ideXlab platform.
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A 0.8 W HDTV Video Processor with simultaneous decoding of two MPEG2 MP@HL streams and capable of 30 frames/s reverse playback
2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), 2002Co-Authors: H. Yamauchi, K. Taketa, Y. Harada, Shigeyuki Okada, Y. Matsuda, T. Mori, Shin'ichiro Okada, T. Watanabe, M. Matsudaira, Y. MatsushitaAbstract:A HDTV Video Processor with decoding/display of two MPEG MP@HL streams and reverse playback with smooth 30 frames/s without frame skip uses a 0.18 /spl mu/m 5-layer process in 6.86/spl times/6.86 mm/sup 2/ and 5.7M transistors. It is for home multimedia and mobile TV applications. It operates at 135 MHz and 0.8 W at 1.8 V.
-
Single chip Video Processor for digital HDTV
ICCE. International Conference on Consumer Electronics (IEEE Cat. No.01CH37182), 2001Co-Authors: H. Yamauchi, S. Okada, K. Taketa, Y. Mihara, Y. HaradaAbstract:We have developed a new high-performance Video system LSI using a 0.25 /spl mu/m CMOS technology for Japan BS digital broadcasting launched in December 2000. The LSI integrates all the necessary functions for Video decoding into a single chip and employs efficient architectures which are parallel processing and have parallel data bus architecture for decoding transport streams efficiently.
-
Single chip Video Processor for digital HDTV
IEEE Transactions on Consumer Electronics, 2001Co-Authors: H. Yamauchi, S. Okada, K. Taketa, Y. Mihara, Y. HaradaAbstract:We have developed a single chip Video Processor integrated TS decoder, MPEG-2 MP@HL decoder and OSD controller for BS digital broadcasting. The Video Processor is available for all the formats of digital broadcasting and displays output on the "Hi-Vision" (high-definition) CRT in SDTV as well as HDTV. Also, 4-channel decoding/display and multi-angle broadcasting of digital TV is obtained. It has excellent functions such as seamless display, audio/Video (AV) synchronization, error concealment, etc. Adoption of a cooperative processing architecture with hardware and software, pipeline architecture and parallel bus architecture allows flexible support of operating frequency reduction, circuit miniaturization, design simplification, high-performance service of BS digital TV, digital TV broadcasting regulation change and equipment specification change. This single chip Video Processor is manufactured of 0.25-/spl mu/m four-layer metal CMOS process and the chip size is 10.2 mm/spl times/10.2 mm. The power consumption is 4.5 W when the supply voltage is 2.5 V and operating frequency is 121.5 MHz.
