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Adaptive Equalizer

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Beomsup Kim – One of the best experts on this subject based on the ideXlab platform.

  • a four channel 3 125 gb s ch cmos serial link transceiver with a mixed mode Adaptive Equalizer
    IEEE Journal of Solid-state Circuits, 2005
    Co-Authors: Jin Wook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S Conroy, Beomsup Kim
    Abstract:

    This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) Adaptive Equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.

Jri Lee – One of the best experts on this subject based on the ideXlab platform.

  • a 20 gb s Adaptive Equalizer in 0 13 muhbox m cmos technology
    IEEE Journal of Solid-state Circuits, 2006
    Co-Authors: Jri Lee
    Abstract:

    An Adaptive Equalizer incorporates spectrum-balancing technique to achieve high speed and low power dissipation. Obviating the need for slicers, this circuit compares the low and high frequency components of the data spectrum and adjusts the boosting accordingly. Fabricated in 0.13-mum CMOS technology, this circuit achieves a data rate of 20 Gb/s while consuming 60mW from a 1.5-V supply

  • a 10gb s cmos Adaptive Equalizer for backplane applications
    International Solid-State Circuits Conference, 2005
    Co-Authors: S Gondi, Jri Lee, D Takeuchi, Behzad Razavi
    Abstract:

    An Equalizer employs reverse scaling and dual-loop adaptation to achieve a binary data rate of 10 Gbit/s. Realized in 0.13 /spl mu/m CMOS technology, the circuit adapts to traces up to 30 inches on FR4 boards while consuming 25 mW from a 1.2 V supply.

Lee-sup Kim – One of the best experts on this subject based on the ideXlab platform.

  • A Data-Pattern-Tolerant Adaptive Equalizer Using the Spectrum Balancing Method
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2010
    Co-Authors: Hye-yoon Joo, Lee-sup Kim
    Abstract:

    This brief presents a data-pattern-tolerant Adaptive Equalizer using the spectrum balancing method. In addition to a high-frequency boost control loop, this Equalizer has a corner frequency control loop to guarantee its accurate adaptation for various data patterns and data rates. Measured results show that the jitter of the eye is reduced by a maximum of 37% when compared to the previous spectrum balancing Equalizer. The chip is fabricated in a 0.18-?m CMOS process, and the Equalizer core occupies 0.35 mm2 and consumes 85 mW.

  • A data pattern-tolerant Adaptive Equalizer using spectrum balancing method
    , 2009
    Co-Authors: Hye-yoon Joo, Lee-sup Kim
    Abstract:

    This paper presents a data pattern-tolerant Adaptive Equalizer using spectrum balancing method. In addition to a high-frequency boosting control loop, this Equalizer has a corner frequency control loop to guarantee its adaptation accuracy for various data patterns and data rates. Measured results show that the jitter of the eye is reduced by maximum 37%. The chip fabrication is based on the 0.18μm CMOS process and the Equalizer core occupies 0.35mm2 and consumes 85mW.

Mohammed Ismail – One of the best experts on this subject based on the ideXlab platform.

  • A low-voltage low-power CMOS analog Adaptive Equalizer for UTP-5 cables
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2008
    Co-Authors: Ahmed Abdelaziz Fayed, Mohammed Ismail
    Abstract:

    An analog Adaptive Equalizer based on a feed-forward architecture is implemented in 0.18-mum digital CMOS process. The Equalizer is implemented with only digital core devices and operates at 125 Mbps over unshielded-twisted-pair category-5 cable of up to 100 m. Novel low-power circuit and system techniques resulted in 3.7-mW total power consumption and supply voltage operation as low as 1.6 V. The maximum peak-to-peak jitter at the output of the Equalizer (including the transmit path driver) under all cable length is 0.33 UI. The total area of the Equalizer is 27738 mum2.

Jin Wook Kim – One of the best experts on this subject based on the ideXlab platform.

  • a four channel 3 125 gb s ch cmos serial link transceiver with a mixed mode Adaptive Equalizer
    IEEE Journal of Solid-state Circuits, 2005
    Co-Authors: Jin Wook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S Conroy, Beomsup Kim
    Abstract:

    This work presents a quad-channel serial-link transceiver providing a maximum full duplex raw data rate of 12.5Gb/s for a single 10-Gbit eXtended Attachment Unit Interface (XAUI) in a standard 0.18-/spl mu/m CMOS technology. To achieve low bit-error rate (BER) and high-speed operation, a mixed-mode least-mean-square (LMS) Adaptive Equalizer and a low-jitter delay-immune clock data recovery (CDR) circuit are used. The transceiver achieves BER lower than <4.5/spl times/10/sup -15/ while its transmitted data and recovered clock have a low jitter of 46 and 64 ps in peak-to-peak, respectively. The chip consumes 178 mW per each channel at 3.125-Gb/s/ch full duplex (TX/RX simultaneous) data rate from 1.8-V power supply.