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P. Balasubramanian - One of the best experts on this subject based on the ideXlab platform.
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Performance Comparison of some Synchronous Adders.
arXiv: Hardware Architecture, 2018Co-Authors: P. BalasubramanianAbstract:This technical note compares the performance of some synchronous Adders which correspond to the following architectures: i) ripple carry adder (RCA), ii) recursive carry lookahead adder (RCLA), iii) hybrid RCLA-RCA with the RCA used in the least significant adder bit positions, iv) block carry lookahead adder (BCLA), v) hybrid BCLA-RCA with the RCA used in the least significant adder bit positions, and vi) non-uniform input partitioned carry select Adders (CSLAs) without and with the binary to excess-1 code (BEC) converter. The 32-bit addition was considered as an example operation. The adder architectures mentioned were implemented by targeting a typical case PVT specification (high threshold voltage, supply voltage of 1.05V and operating temperature of 25 degrees Celsius) of the Synopsys 32/28nm CMOS technology. The comparison leads to the following observations: i) the hybrid CCLA-RCA is preferable to the other Adders in terms of the speed, the power-delay product, and the energy-delay product, ii) the non-uniform input partitioned CSLA without the BEC converter is preferable to the other Adders in terms of the area-delay product, and iii) the RCA incorporating the full adder present in the standard digital cell library is preferable to the other Adders in terms of the power-delay-area product.
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area latency optimized early output asynchronous full Adders and relative timed ripple carry Adders
arXiv: Hardware Architecture, 2016Co-Authors: P. Balasubramanian, S. YamashitaAbstract:This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full Adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full Adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full Adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full Adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full Adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology.
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Area/latency optimized early output asynchronous full Adders and relative-timed ripple carry Adders
SpringerPlus, 2016Co-Authors: P. Balasubramanian, S. YamashitaAbstract:This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full Adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full Adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full Adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full Adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full Adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology.
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fpga based synthesis of high speed hybrid carry select Adders
Advances in Optoelectronics, 2015Co-Authors: V Kokilavani, K Preethi, P. BalasubramanianAbstract:Carry select adder is a square-root time high-speed adder. In this paper, FPGA-based synthesis of conventional and hybrid carry select Adders are described with a focus on high speed. Conventionally, carry select Adders are realized using the following: (i) full Adders and 2 : 1 multiplexers, (ii) full Adders, binary to excess 1 code converters, and 2 : 1 multiplexers, and (iii) sharing of common Boolean logic. On the other hand, hybrid carry select Adders involve a combination of carry select and carry lookahead Adders with/without the use of binary to excess 1 code converters. In this work, two new hybrid carry select Adders are proposed involving the carry select and section-carry based carry lookahead subAdders with/without binary to excess 1 converters. Seven different carry select Adders were implemented in Verilog HDL and their performances were analyzed under two scenarios, dual-operand addition and multioperand addition, where individual operands are of sizes 32 and 64-bits. In the case of dual-operand additions, the hybrid carry select adder comprising the proposed carry select and section-carry based carry lookahead configurations is the fastest. With respect to multioperand additions, the hybrid carry select adder containing the carry select and conventional carry lookahead or section-carry based carry lookahead structures produce similar optimized performance.
Earl E Swartzlander - One of the best experts on this subject based on the ideXlab platform.
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memristor based adder circuit design
Asilomar Conference on Signals Systems and Computers, 2016Co-Authors: Nagaraja Revanna, Earl E SwartzlanderAbstract:Memristors are non-volatile memory elements. In applications like mem-computing, where memory acts both as a site for storing data and logic computations, memristors provide promising future. In this paper, the design of Adders implemented with memristors is discussed. Memristor based designs for standard fixed point adder architectures (ripple carry adder, carry look-ahead adder and parallel prefix Adders) are explained. The area and latency are compared. Surprisingly, the Radix-2 CLA has a complexity very similar to the parallel prefix Adders. It is shown that the Kogge-Stone design has the best metric in terms of delay and area among the parallel prefix Adders.
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implementation of a high speed multiplier using carry lookahead Adders
Asilomar Conference on Signals Systems and Computers, 2013Co-Authors: Wesley Chu, Ali I Unwala, Earl E SwartzlanderAbstract:This paper examines a modification to the Wallace/Dadda Multiplier to use carry lookahead Adders instead of full Adders to implement the reduction of the bit product matrix into the two numbers that are summed to make the product. Four bit carry lookahead Adders are used in the reduction in place of individual full Adders. Each carry lookahead adder reduces up to 9 partial products (instead of 3 with a full adder) while taking the same amount of time. This leads to fewer reduction stages than a traditional Wallace/Dadda Multiplier. The results show that 1 fewer stage is required for 4 by 4, 8 by 8, and 16 by 16 bit multipliers and 2 stages are saved for larger multipliers.
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Implementation of a speculative Ling adder
Mathematics for Signal and Information Processing, 2009Co-Authors: Malhar Mehta, Amith Kumar Nuggehalli Ramachandra, Earl E SwartzlanderAbstract:A large number of adder designs are available based on the constraints of a particular application, e.g., speed, fanout, wire complexity, area, power consumption, etc. However, a lower-bound has been set on the speed of these Adders and it has not been possible to design reliable Adders faster than this lower bound. This paper deals with the design and implementation of a speculative adder, that takes advantage of the probabilistic dependence of the maximum carrypropagate chain length on the adder operand size. That is, this type of adder is designed to produce correct results for a vast majority of inputs that have carry-propagate chains shorter than the length for which the adder has been designed. An improvement is proposed to an earlier design of a speculative adder, by using Ling equations to speed it up. The resulting speculative adder, called the ACLA has been compared with the earlier design and traditional Adders like Ling and Kogge-Stone in terms of area, delay and number of gates required. The ACLA is at least 9.8% faster and 20% smaller than the previous design. A circuit for error detection and error correction has also been implemented, resulting in the Reliable Adder (RA). When implemented as a sequential circuit, such a combination of ACLA and RA can significantly increase the average speed of the adder unit.
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Optimization of spanning tree Adders
Advanced Signal Processing Algorithms Architectures and Implementations XVI, 2006Co-Authors: Megha Ladha, Earl E SwartzlanderAbstract:This paper compares several designs of spanning tree Adders for 16 and 32 bit widths. The carry select part of the spanning tree is done using ripple carry and carry skip Adders (4, 8 and 16 bits) and compared in terms of delay, complexity and power consumption. The spanning tree design is also compared with that of a conventional carry lookahead adder. All the designs are done using only 2 input NAND and NOR gates and inverters in 0.18 μm CMOS technology. The delay and power consumption is determined by use of simulations performed with Synopsys and Cadence design tools. The spanning tree adder realized with carry skip Adders is about 40% faster than the carry lookahead adder with an approximate increase of 17% in complexity and 22% in power.
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Variable spanning tree adder
Conference Record of The Twenty-Ninth Asilomar Conference on Signals Systems and Computers, 1Co-Authors: R.h. Nigaglioni, Earl E SwartzlanderAbstract:This paper presents the design of the constant and variable spanning tree Adders, 64 bit Adders based on the spanning tree adder and the recursive hybrid adder. Manchester carry chains of various lengths are used to optimize the designs. The intermediate outputs of the carry chain used in the spanning tree adder are eliminated. A comparison of the delay and complexity of the spanning tree adder, the recursive hybrid adder and the two new Adders shows that the delays are less for the new Adders while the complexities are between that of the spanning tree adder and the recursive hybrid adder.
B. Rajeshwar - One of the best experts on this subject based on the ideXlab platform.
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A New Design for Variable Latency Speculative E.C&D Han-Carlson Adder
International Journal of Research, 2017Co-Authors: K . Karthik, B. RajeshwarAbstract:Variable latency Adders have been recently proposed in literature. In variable latency adder unwanted interconnections also reduced compared with kogge-stone topology. Kogge-Stone adder consists of large number of black cells and many wire tracks. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time, but not always. In order to detect the error, error detection network is also used. The approximated adder is augmented with an error detection network that asserts an error signal when speculation fails. Speculative variable latency Adders to reduce average delay compared to traditional architectures. This paper proposes a novel variable latency speculative adder based on Han-Carlson parallel- prefix topology which proposes the error detection network that reduces error probability compared to previous approaches. Several variable latency speculative Adders, for various operand lengths, using both Han-Carlson and Kogge- Stone topology, have been synthesized using Xilinx 14.3. Obtained results show that proposed variable latency Han-Carlson adder used in high-speed application.
S. Yamashita - One of the best experts on this subject based on the ideXlab platform.
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area latency optimized early output asynchronous full Adders and relative timed ripple carry Adders
arXiv: Hardware Architecture, 2016Co-Authors: P. Balasubramanian, S. YamashitaAbstract:This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full Adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full Adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full Adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full Adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full Adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology.
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Area/latency optimized early output asynchronous full Adders and relative-timed ripple carry Adders
SpringerPlus, 2016Co-Authors: P. Balasubramanian, S. YamashitaAbstract:This article presents two area/latency optimized gate level asynchronous full adder designs which correspond to early output logic. The proposed full Adders are constructed using the delay-insensitive dual-rail code and adhere to the four-phase return-to-zero handshaking. For an asynchronous ripple carry adder (RCA) constructed using the proposed early output full Adders, the relative-timing assumption becomes necessary and the inherent advantages of the relative-timed RCA are: (1) computation with valid inputs, i.e., forward latency is data-dependent, and (2) computation with spacer inputs involves a bare minimum constant reverse latency of just one full adder delay, thus resulting in the optimal cycle time. With respect to different 32-bit RCA implementations, and in comparison with the optimized strong-indication, weak-indication, and early output full adder designs, one of the proposed early output full Adders achieves respective reductions in latency by 67.8, 12.3 and 6.1 %, while the other proposed early output full adder achieves corresponding reductions in area by 32.6, 24.6 and 6.9 %, with practically no power penalty. Further, the proposed early output full Adders based asynchronous RCAs enable minimum reductions in cycle time by 83.4, 15, and 8.8 % when considering carry-propagation over the entire RCA width of 32-bits, and maximum reductions in cycle time by 97.5, 27.4, and 22.4 % for the consideration of a typical carry chain length of 4 full adder stages, when compared to the least of the cycle time estimates of various strong-indication, weak-indication, and early output asynchronous RCAs of similar size. All the asynchronous full Adders and RCAs were realized using standard cells in a semi-custom design fashion based on a 32/28 nm CMOS process technology.
K . Karthik - One of the best experts on this subject based on the ideXlab platform.
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A New Design for Variable Latency Speculative E.C&D Han-Carlson Adder
International Journal of Research, 2017Co-Authors: K . Karthik, B. RajeshwarAbstract:Variable latency Adders have been recently proposed in literature. In variable latency adder unwanted interconnections also reduced compared with kogge-stone topology. Kogge-Stone adder consists of large number of black cells and many wire tracks. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time, but not always. In order to detect the error, error detection network is also used. The approximated adder is augmented with an error detection network that asserts an error signal when speculation fails. Speculative variable latency Adders to reduce average delay compared to traditional architectures. This paper proposes a novel variable latency speculative adder based on Han-Carlson parallel- prefix topology which proposes the error detection network that reduces error probability compared to previous approaches. Several variable latency speculative Adders, for various operand lengths, using both Han-Carlson and Kogge- Stone topology, have been synthesized using Xilinx 14.3. Obtained results show that proposed variable latency Han-Carlson adder used in high-speed application.
