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Said Hamdioui – One of the best experts on this subject based on the ideXlab platform.

  • hardware based aging mitigation scheme for memory Address Decoder
    European Test Symposium, 2019
    Co-Authors: Daniel Kraak, Said Hamdioui, Innocent Agbo, Mottaqiallah Taouil, Pieter Weckx, Stefan Cosemans, Francky Catthoor
    Abstract:

    Designers typically add design margins to memories to compensate for their aging. As the aging impact increases with technology scaling, bigger margins become necessary. However, this negatively impacts area, yield, performance, and power consumption. Alternatively, mitigation schemes can be used to reduce the impact of aging. This paper proposes a hardware-based mitigation scheme for the memory’s Address Decoder logic. The scheme is based on adapting the Decoder‘s workload during idle cycles by stressing the short paths and putting long paths into relaxation. Thanks to the adapted workload, the impact of aging on the Address Decoder is reduced, resulting in a more reliable memory. To validate the benefit of the mitigation scheme, the Decoder‘s degradation of the L1 data and instruction caches for an ARM v8-a processor is analyzed. The experimental results show that the proposed mitigation scheme reduces the degradation of the Decoder‘s timing margin with up to 4.1x at negligible area and no more than 3% power overhead.

  • software based mitigation for memory Address Decoder aging
    2019 IEEE Latin American Test Symposium (LATS), 2019
    Co-Authors: Daniel Kraak, Cemil Cem Gursoy, Innocent Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui
    Abstract:

    Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary to achieve the desired reliability. However, these increased margins lead to a reduced performance and lower yield. Alternatively, mitigation schemes can be deployed to reduce the aging. This paper proposes a software-based method to mitigate the aging of the memory’s Address Decoder logic due to Bias Temperature Instability. The method is based on periodically applying a rejuvenation application on top of a user application. The goal of the rejuvenation application is to recover aged transistors of the critical paths of the Address Decoder. The experimental results show that the proposed method significantly reduces aging in cases when applications consist of memory access patterns that result in an unbalanced stress in the Address Decoder logic. In particular, it reduces the degradation of the Address Decoder’s setup delay by up to 43% with an execution overhead of only 1%.

  • LATS – Software-Based Mitigation for Memory Address Decoder Aging
    2019 IEEE Latin American Test Symposium (LATS), 2019
    Co-Authors: Daniel Kraak, Cemil Cem Gursoy, Innocent Agbo, Mottaqiallah Taouil, Maksim Jenihhin, Jaan Raik, Said Hamdioui
    Abstract:

    Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary to achieve the desired reliability. However, these increased margins lead to a reduced performance and lower yield. Alternatively, mitigation schemes can be deployed to reduce the aging. This paper proposes a software-based method to mitigate the aging of the memory’s Address Decoder logic due to Bias Temperature Instability. The method is based on periodically applying a rejuvenation application on top of a user application. The goal of the rejuvenation application is to recover aged transistors of the critical paths of the Address Decoder. The experimental results show that the proposed method significantly reduces aging in cases when applications consist of memory access patterns that result in an unbalanced stress in the Address Decoder logic. In particular, it reduces the degradation of the Address Decoder’s setup delay by up to 43% with an execution overhead of only 1%.

Arnaud Virazel – One of the best experts on this subject based on the ideXlab platform.

  • An effective BIST architecture for power-gating mechanisms in low-power SRAMs
    , 2016
    Co-Authors: Alberto Bosio, Patrick Girard, Arnaud Virazel, Luigi Dilillo, Leonardo B. Zordan
    Abstract:

    In low-power SRAMs, power-gating mechanisms are commonly used to reduce static powepower consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting-off one or more memory blocks (core-cell array, Address Decoder, I/O logic, etc), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we present an efficient Built-In-Self-Test architecture targeting defects affecting power-gating circuitry in low-power SRAMs. Experimental results show that the proposed solution improves the defect coverage and thus, it significantly increases the overall test quality compared to the state-of-the-art.

  • On the Test and Mitigation of Malfunctions in Low-Power SRAMs
    Journal of Electronic Testing, 2014
    Co-Authors: Leonardo B. Zordan, Patrick Girard, Arnaud Virazel, Luigi Dilillo, Alberto Bosio, Nabil Badereddine
    Abstract:

    In low-power SRAMs, power gating mechanisms are commonly used to reduce static powepower consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting off one or more memory blocks (core-cell array, Address Decoder, I/O logic, etc.), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we first present a detailed analysis based on electrical simulations to identify faulty behaviors caused by realistic defects that may affect power gating mechanisms embedded in low-power SRAMs. Based on this analysis, we present an efficient test solution targeting detection of observed faulty behaviors. As a final contribution, we propose novel techniques to mitigate the impact of studied defects, once detected by test methods, therefore providing significant yield improvement.

  • Resistive-Open Defects in Address Decoders
    Advanced Test Methods for SRAMs, 2009
    Co-Authors: Patrick Girard, Serge Pravossoudovitch, Luigi Dilillo, Alberto Bosio, Arnaud Virazel
    Abstract:

    This chapter targets the study of dynamic faults that affect the Address Decoders of SRAMs, in particular ADOFs (Address Decoder Open Faults) and resistive-ADOFs that are caused by intra-gate pure open and resistive-open defects. Experiments show that resistive-ADOFs, which are a generalization of ADOFs, require more stringent timing constraints for their sensitization. Several algorithmic solutions are effective to test these faults. These so-lutions are mainly based on the ‘Sachdev’s pattern.’ One of these test solutions consists in a compact 2 N March test that can be em-bedded in existing March tests, without modifying their complexity and their capability to cover the former target faults. A meaningful example of a modified test algorithm covering ADOFs is March iC-, which is an improved version of March C-.

Patrick Girard – One of the best experts on this subject based on the ideXlab platform.

  • An effective BIST architecture for power-gating mechanisms in low-power SRAMs
    , 2016
    Co-Authors: Alberto Bosio, Patrick Girard, Arnaud Virazel, Luigi Dilillo, Leonardo B. Zordan
    Abstract:

    In low-power SRAMs, power-gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting-off one or more memory blocks (core-cell array, Address Decoder, I/O logic, etc), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we present an efficient Built-In-Self-Test architecture targeting defects affecting power-gating circuitry in low-power SRAMs. Experimental results show that the proposed solution improves the defect coverage and thus, it significantly increases the overall test quality compared to the state-of-the-art.

  • On the Test and Mitigation of Malfunctions in Low-Power SRAMs
    Journal of Electronic Testing, 2014
    Co-Authors: Leonardo B. Zordan, Patrick Girard, Arnaud Virazel, Luigi Dilillo, Alberto Bosio, Nabil Badereddine
    Abstract:

    In low-power SRAMs, power gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting off one or more memory blocks (core-cell array, Address Decoder, I/O logic, etc.), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we first present a detailed analysis based on electrical simulations to identify faulty behaviors caused by realistic defects that may affect power gating mechanisms embedded in low-power SRAMs. Based on this analysis, we present an efficient test solution targeting detection of observed faulty behaviors. As a final contribution, we propose novel techniques to mitigate the impact of studied defects, once detected by test methods, therefore providing significant yield improvement.

  • Resistive-Open Defects in Address Decoders
    Advanced Test Methods for SRAMs, 2009
    Co-Authors: Patrick Girard, Serge Pravossoudovitch, Luigi Dilillo, Alberto Bosio, Arnaud Virazel
    Abstract:

    This chapter targets the study of dynamic faults that affect the Address Decoders of SRAMs, in particular ADOFs (Address Decoder Open Faults) and resistive-ADOFs that are caused by intra-gate pure open and resistive-open defects. Experiments show that resistive-ADOFs, which are a generalization of ADOFs, require more stringent timing constraints for their sensitization. Several algorithmic solutions are effective to test these faults. These so-lutions are mainly based on the ‘Sachdev’s pattern.’ One of these test solutions consists in a compact 2 N March test that can be em-bedded in existing March tests, without modifying their complexity and their capability to cover the former target faults. A meaningful example of a modified test algorithm covering ADOFs is March iC-, which is an improved version of March C-.

Luigi Dilillo – One of the best experts on this subject based on the ideXlab platform.

  • An effective BIST architecture for power-gating mechanisms in low-power SRAMs
    , 2016
    Co-Authors: Alberto Bosio, Patrick Girard, Arnaud Virazel, Luigi Dilillo, Leonardo B. Zordan
    Abstract:

    In low-power SRAMs, power-gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting-off one or more memory blocks (core-cell array, Address Decoder, I/O logic, etc), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we present an efficient Built-In-Self-Test architecture targeting defects affecting power-gating circuitry in low-power SRAMs. Experimental results show that the proposed solution improves the defect coverage and thus, it significantly increases the overall test quality compared to the state-of-the-art.

  • On the Test and Mitigation of Malfunctions in Low-Power SRAMs
    Journal of Electronic Testing, 2014
    Co-Authors: Leonardo B. Zordan, Patrick Girard, Arnaud Virazel, Luigi Dilillo, Alberto Bosio, Nabil Badereddine
    Abstract:

    In low-power SRAMs, power gating mechanisms are commonly used to reduce static power consumption. When the SRAM is not accessed for a long period, such mechanisms allow shutting off one or more memory blocks (core-cell array, Address Decoder, I/O logic, etc.), thus reducing leakage currents. In order to guarantee static power reduction in low-power SRAMs, reliable operation of power gating mechanisms must be ensured by adequate test techniques. In this paper, we first present a detailed analysis based on electrical simulations to identify faulty behaviors caused by realistic defects that may affect power gating mechanisms embedded in low-power SRAMs. Based on this analysis, we present an efficient test solution targeting detection of observed faulty behaviors. As a final contribution, we propose novel techniques to mitigate the impact of studied defects, once detected by test methods, therefore providing significant yield improvement.

  • Resistive-Open Defects in Address Decoders
    Advanced Test Methods for SRAMs, 2009
    Co-Authors: Patrick Girard, Serge Pravossoudovitch, Luigi Dilillo, Alberto Bosio, Arnaud Virazel
    Abstract:

    This chapter targets the study of dynamic faults that affect the Address Decoders of SRAMs, in particular ADOFs (Address Decoder Open Faults) and resistive-ADOFs that are caused by intra-gate pure open and resistive-open defects. Experiments show that resistive-ADOFs, which are a generalization of ADOFs, require more stringent timing constraints for their sensitization. Several algorithmic solutions are effective to test these faults. These so-lutions are mainly based on the ‘Sachdev’s pattern.’ One of these test solutions consists in a compact 2 N March test that can be em-bedded in existing March tests, without modifying their complexity and their capability to cover the former target faults. A meaningful example of a modified test algorithm covering ADOFs is March iC-, which is an improved version of March C-.

Serge Pravossoudovitch – One of the best experts on this subject based on the ideXlab platform.

  • Resistive-Open Defects in Address Decoders
    Advanced Test Methods for SRAMs, 2009
    Co-Authors: Patrick Girard, Serge Pravossoudovitch, Luigi Dilillo, Alberto Bosio, Arnaud Virazel
    Abstract:

    This chapter targets the study of dynamic faults that affect the Address Decoders of SRAMs, in particular ADOFs (Address Decoder Open Faults) and resistive-ADOFs that are caused by intra-gate pure open and resistive-open defects. Experiments show that resistive-ADOFs, which are a generalization of ADOFs, require more stringent timing constraints for their sensitization. Several algorithmic solutions are effective to test these faults. These so-lutions are mainly based on the ‘Sachdev’s pattern.’ One of these test solutions consists in a compact 2 N March test that can be em-bedded in existing March tests, without modifying their complexity and their capability to cover the former target faults. A meaningful example of a modified test algorithm covering ADOFs is March iC-, which is an improved version of March C-.

  • New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories
    Journal of Integrated Circuits and Systems, 2008
    Co-Authors: Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-hassan
    Abstract:

    This paper presents a complete analysis of the ability of March tests to detect ADOFs (Address Decoder Open Faults) and resistive-ADOFs in Address Decoders of embedded-SRAMs. Such faults are the primary target of this study because they are notoriously hard-to-detect. With this study, we show that standard March tests without modifications are not able to detect them and we propose to translate the algorithm presented in [1, 2] into March elements. These new March elements involve a particular Address sequence and data to be written. For this purpose, we have exploited some Degrees of Freedom of the March tests (DOF I and IV) in order to generate these new March elements for ADOFs detection. Compared to the previous March solutions, these new March elements ensure the fault observation.

  • A concurrent approach for testing Address Decoder faults in eFlash memories
    2007 IEEE International Test Conference, 2007
    Co-Authors: Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean-michel Daga
    Abstract:

    The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we Address a major issue during eFlash testing, namely the test of Address Decoder Faults (AFs), which is generally very time consuming with ad-hoc solutions presently used in industry. In the first part of the paper, we show the impact of AFs on the functional behavior of an eFlash. Next, we use an analogy with RAM memory testing to classify AFs with respect to their functional behavior. We then obtain AFs acting either as stuck-at faults or as state coupling faults. In the fourth part of the paper, we propose a concurrent approach for testing AFs acting on either the word line Decoder or the bit line Decoder. The proposed approach allows using a minimal number of programming operations during test application. Finally, we propose a compaction procedure to further reduce the test time of AFs. As a result, huge reductions in test time can be achieved; experiments on a 4 Mbits eFlash have shown that a test time reduction factor of 34x can be obtained when compared to the global eFlash test flow presently used in industry. An additional important feature of the proposed strategy is that it allows testing 100% of other critical faults in eFlashs (stuck-at, transition and state coupling faults) beside full coverage of AFs.