The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
SANG HYEON BAEG - One of the best experts on this subject based on the ideXlab platform.
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resource efficient sram based ternary content Addressable Memory
IEEE Transactions on Very Large Scale Integration Systems, 2017Co-Authors: Ali Ahmed, Kyungbae Park, SANG HYEON BAEGAbstract:Static random access Memory (SRAM)-based ternary content Addressable Memory (TCAM) offers TCAM functionality by emulating it with SRAM. However, this emulation suffers from reduced Memory efficiency while mapping the TCAM table on SRAM units. This is due to the limited capacity of the physical addresses in the SRAM unit. This brief offers a novel Memory architecture called a resource-efficient SRAM-based TCAM (REST), which emulates TCAM functionality using optimal resources. The SRAM unit is divided into multiple virtual blocks to store the address information presented in the TCAM table. This approach virtually increases the overall address space of the SRAM unit, mapping a greater portion of the TCAM table in SRAM and increasing the overall emulated TCAM bits/SRAM at the cost of reduced throughput. A $72 \times 28$ -bit REST consumes only one 36-kbit SRAM and a few distributed RAMs via implementation on a Xilinx Kintex-7 field-programmable gate array. It uses only 3.5% of the Memory resources compared with a conventional SRAM-based TCAM (hybrid-partitioned TCAM).
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Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory
IEEE Transactions on Circuits and Systems, 2012Co-Authors: Zahid Ullah, SANG HYEON BAEGAbstract:Although content Addressable Memory (CAM) provides fast search operation; however, CAM has disadvantages like low bit density and high cost per bit. This paper presents a novel Memory architecture called hybrid partitioned static random access Memory-based ternary content Addressable Memory (HP SRAM-based TCAM), which emulates TCAM functionality with conventional SRAM, thereby eliminating the inherited disadvantages of conventional TCAMs. HP SRAM-based TCAM logically dissects conventional TCAM table in a hybrid way (column-wise and row-wise) into TCAM sub-tables, which are then processed to be mapped to their corresponding SRAM Memory units. Search operation in HP SRAM-based TCAM involves two SRAM accesses followed by a logical ANDing operation. To validate and justify our approach, 512 × 36 HP SRAM-based TCAM has been implemented in Xilinx Virtex-5 field programmable gate array (FPGA) and designed using 65-nm CMOS technology. Implementation in FPGA is advantageous and a beauty of our proposed TCAM because classical TCAMs cannot be implemented in FPGA. After a thorough analysis, we have concluded that energy/bit/search of the proposed TCAM is 85.72 fJ.
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Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line
IEEE Transactions on Circuits and Systems I: Regular Papers, 2008Co-Authors: SANG HYEON BAEGAbstract:Power consumption in match lines is the most critical issue for low-power ternary content-Addressable Memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by sharing the charges deposited in various parts of the partitioned segments. This arrangement reduces the match-line power consumption by reducing effective capacitor loading and voltage swing at match lines. The segmented architecture also enhances operational speed by evaluating multiple segments in parallel and by overlapping the pre-charging and evaluation stages. 512 times 72 TCAM is designed using 0.18-mum CMOS technology. The extracted RC values are used to show the power reduction benefits. The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM. The power savings by segmenting match lines can be up to 41% over a low-voltage swing technique due to the independent discharge capability in segmented match-line architecture.
Ali Sheikholeslami - One of the best experts on this subject based on the ideXlab platform.
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content Addressable Memory cam circuits and architectures a tutorial and survey
IEEE Journal of Solid-state Circuits, 2006Co-Authors: K Pagiamtzis, Ali SheikholeslamiAbstract:We survey recent developments in the design of large-capacity content-Addressable Memory (CAM). A CAM is a Memory that implements the lookup-table function in a single clock cycle using dedicated comparison circuitry. CAMs are especially popular in network routers for packet forwarding and packet classification, but they are also beneficial in a variety of other applications that require high-speed table lookup. The main CAM-design challenge is to reduce power consumption associated with the large amount of parallel active circuitry, without sacrificing speed or Memory density. In this paper, we review CAM-design techniques at the circuit level and at the architectural level. At the circuit level, we review low-power matchline sensing techniques and searchline driving approaches. At the architectural level we review three methods for reducing power consumption.
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a low power content Addressable Memory cam using pipelined hierarchical search scheme
IEEE Journal of Solid-state Circuits, 2004Co-Authors: K Pagiamtzis, Ali SheikholeslamiAbstract:This paper presents two techniques to reduce power consumption in content-Addressable memories (CAMs). The first technique is to pipeline the search operation by breaking the match-lines into several segments. Since most stored words fail to match in their first segments, the search operation is discontinued for subsequent segments, hence reducing power. The second technique is to broadcast small-swing search data on less capacitive global search-lines, and only amplify this signal to full swing on a shorter local search-line. As few match-line segments are active, few local search-lines will be enabled, again saving power. We have employed the proposed schemes in a 1024/spl times/144-bit ternary CAM in 1.8-V 0.18-/spl mu/m CMOS, illustrating an overall power reduction of 60% compared to a nonpipelined, nonhierarchical architecture. The ternary CAM achieves a 7-ns search cycle time at 2.89fJ/bit/search.
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a mismatch dependent power allocation technique for match line sensing in content Addressable memories
IEEE Journal of Solid-state Circuits, 2003Co-Authors: Igor Arsovski, Ali SheikholeslamiAbstract:In the conventional content-Addressable Memory (CAM), equal power is consumed to determine if a stored word is matched to a search word or mismatched, independent of the number of mismatched bits. This paper presents a match-line (ML) sensing scheme that allocates less power to match decisions involving a larger number of mismatched bits. Since the majority of CAM words are mismatched, this scheme results in a significant CAM power reduction. The proposed ML sensing scheme is implemented in a 256 /spl times/ 144-bit ternary CAM for a 0.13-/spl mu/m 1.2-V CMOS logic process. For a 2-ns search time on a 144-bit word, the proposed scheme saves 60% of the power consumed by the conventional sensing scheme.
Zahid Ullah - One of the best experts on this subject based on the ideXlab platform.
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g aetcam gate based area efficient ternary content Addressable Memory on fpga
IEEE Access, 2017Co-Authors: Muhammad Irfan, Zahid UllahAbstract:This paper presents a novel architecture for ternary content-Addressable Memory (TCAM), using G-AETCAM cells, which outputs the address of the provided input data. The proposed architecture is a matrix of G-AETCAM cells arranged in the form of rows and columns using flip-flop as a Memory element and a control logic circuitry consisting of logic gates. One G-AETCAM cell encodes the input and stored bit into one encoded bit which results in a match-line after passing from the AND-gate-array. Many architectures configure random-access Memory (RAM) available on FPGAs as content-Addressable storage architecture but are efficient for specific size and deal with data only in ascending or descending order while the proposed architecture provides freedom in size with no chance of making a single Memory cell as useless and can store ternary data in any order. RAM-based TCAMs require pre-processing for the storage of TCAM words while the proposed design does not involve any pre-processing. The proposed architecture reduces the transistor count by a factor of 25.55, as compared with the RAM-based TCAM, which ultimately reduces area and increases the speed of operations. The proposed architecture is successfully implemented on Xilinx Virtex-6 FPGA for the size $64\times 36$ and achieves a speed of 358 MHz.
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Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory
IEEE Transactions on Circuits and Systems, 2012Co-Authors: Zahid Ullah, SANG HYEON BAEGAbstract:Although content Addressable Memory (CAM) provides fast search operation; however, CAM has disadvantages like low bit density and high cost per bit. This paper presents a novel Memory architecture called hybrid partitioned static random access Memory-based ternary content Addressable Memory (HP SRAM-based TCAM), which emulates TCAM functionality with conventional SRAM, thereby eliminating the inherited disadvantages of conventional TCAMs. HP SRAM-based TCAM logically dissects conventional TCAM table in a hybrid way (column-wise and row-wise) into TCAM sub-tables, which are then processed to be mapped to their corresponding SRAM Memory units. Search operation in HP SRAM-based TCAM involves two SRAM accesses followed by a logical ANDing operation. To validate and justify our approach, 512 × 36 HP SRAM-based TCAM has been implemented in Xilinx Virtex-5 field programmable gate array (FPGA) and designed using 65-nm CMOS technology. Implementation in FPGA is advantageous and a beauty of our proposed TCAM because classical TCAMs cannot be implemented in FPGA. After a thorough analysis, we have concluded that energy/bit/search of the proposed TCAM is 85.72 fJ.
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FPGA Implementation of SRAM-based Ternary Content Addressable Memory
2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012Co-Authors: Zahid Ullah, Manish Kumar Jaiswal, Y.c. Chan, Ray C.c. CheungAbstract:Content Addressable Memory (CAM) is a special Memory that accomplishes search operation in a single clock cycle but CAM has disadvantages like low bit density and high cost per bit. In this paper, we present an implementation of a 512 x 36 SRAM-based TCAM (SR-TCAM) on a Virtex-5 FPGA, which is the strength of SR-TCAM because currently classical TCAMs cannot be implemented on FPGA. We have used two synthesis optimizations (BRAM-AUTO and BRAM = BLOCK_POWER2) using BRAMs on FPGA. Thus, user can choose design parameters that are suitable for his application. The power data has been measured using Xilinx X-Power by using activities for search operations of SR-TCAM. We have computed power consumption by taking the average of 1000 search operations with 100 MHz clock speed to have better power estimation, which results, for one of the design, in an average power consumption of 2.11 mW. SR-TCAM exploits dense SRAM and achieves comparable search performance in two clock cycles. Thus, SR-TCAM is a feasible and practical alternative to traditional CAMs.
Shoun Matsunaga - One of the best experts on this subject based on the ideXlab platform.
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fabrication of a 99 energy less nonvolatile multi functional cam chip using hierarchical power gating for a massively parallel full text search engine
Symposium on VLSI Circuits, 2013Co-Authors: Shoun Matsunaga, H. Honjo, S. Miura, Ryusuke Nebashi, Noboru Sakimura, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Keizo Kinoshita, H SatoAbstract:A ternary content-Addressable Memory (TCAM)-based hardware called nonvolatile “multi-functional CAM (MF-CAM)” is proposed for an ultra-low-energy “full-text search” system in recent data centers. The proposed nonvolatile MF-CAM-based full-text search engine can perform parallel comparison while eliminating leakage energy by hierarchical power gating. By the massively parallel comparison with the hierarchical power gating, energy consumption of the proposed search engine is reduced within 1% in comparison with the conventional CPU-based full-text search system, where repetitive comparisons between the CPU and a Memory consume much energy.
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high throughput low energy content Addressable Memory based on self timed overlapped search mechanism
IEEE International Symposium on Asynchronous Circuits and Systems, 2012Co-Authors: Naoya Onizawa, Shoun Matsunaga, Vincent Gaudet, Takahiro HanyuAbstract:This paper introduces a self-timed overlapped search mechanism for high-throughput content-Addressable memories (CAMs) with low search energy. Most mismatches can be found by searching the first few bits in a search word. Consequently, if a word circuit is divided into two sections that are sequentially searched, most match lines in the second section are unused. As searching the first section is faster than searching an entire word, we could potentially increase throughput by initiating a second-stage search on the unused match lines as soon as a first-stage search is complete. The overlapped search mechanism is realized using a self-timed word circuit that is independently controlled by a locally generated control signal, reducing the power dissipation of global clocking. A 256 x 144-bit CAM is designed under in 90 nm CMOS that operates with 5.57x faster throughput than a synchronous CAM, with 38% energy saving and 8% area overhead.
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design of a 270ps access 7 transistor 2 magnetic tunnel junction cell circuit for a high speed search nonvolatile ternary content Addressable Memory
Journal of Applied Physics, 2012Co-Authors: Shoun Matsunaga, Tetsuo Endoh, H Ohno, Akira Katsumata, Masanori Natsui, Takahiro HanyuAbstract:A novel 7-transistor/2-magnetic-tunnel-junction (7 T-2MTJ) cell circuit is proposed for a high-speed and compact nonvolatile ternary content-Addressable Memory (TCAM). Since critical path for switching in the TCAM cell circuit, which determines the performance of the TCAM, is only a single MOS transistor, switching delay of the TCAM word circuit is minimized. As a result, 270 ps of switching delay in 144-bit TCAM word circuit is achieved under a 90 nm CMOS/MTJ technology with magneto-resistance ratio of 100%, which is about two times faster than a conventional CMOS-based TCAM.
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standby power free compact ternary content Addressable Memory cell chip using magnetic tunnel junction devices
Applied Physics Express, 2009Co-Authors: Shoun Matsunaga, Shoji Ikeda, K Miura, Jun Hayakawa, Tetsuo Endoh, Kimiyuki Hiyama, Atsushi Matsumoto, Haruhiro Hasegawa, H OhnoAbstract:A compact ternary content-Addressable Memory (TCAM) cell of 3.15 µm2 with a 0.14 µm complementary metal oxide semiconductor process is realized by the use of nonvolatile magnetic tunnel junction (MTJ) devices with spin-injection write. This TCAM cell based on logic-in-Memory architecture with nonvolatile MTJs needs no standby power, yet allows instant shut-down of the supply voltage without data backup to an external nonvolatile device.
Y Mori - One of the best experts on this subject based on the ideXlab platform.
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a design for high speed low power cmos fully parallel content Addressable Memory macros
IEEE Journal of Solid-state Circuits, 2001Co-Authors: Hisatada Miyatake, M Tanaka, Y MoriAbstract:Described is a design for high-speed low-power-consumption fully parallel content-Addressable Memory (CAM) macros for CMOS ASIC applications. The design supports configurations ranging from 64 words by 8 bits to 2048 words by 64 bits and achieves around 7.5-ns search access times in CAM macros on a 0.35-/spl mu/m 3.3-V standard CMOS ASIC technology. A new CAM cell with a pMOS match-line driver reduces search rush current and power consumption, allowing a NOR-type match-line structure suitable for high-speed search operations. It is also shown that the CAM cell has other advantages that lead to a simple high-speed current-saving architecture. A small signal on the match line is detected by a single-ended sense amplifier which has both high-speed and low-power characteristics and a latch function. The same type of sense amplifier is used for a fast read operation, realizing 5-ns access time under typical conditions. For further current savings in search operations, the precharging of the match line is controlled based on the valid bit status. Also, a dual bit switch with optimized size and control reduces the current. CAM macros of 256/spl times/54 configuration on test chips showed 7.3-ns search access time with a power-performance metric of 131 fJ/bit/search under typical conditions.